Artyom Skrobov b43981076a [ARM] Allow SP in rGPR, starting from ARMv8 ... Summary: This patch handles assembly and disassembly, but not codegen, as of yet. Additionally, it fixes a bug whereby SP and PC as shifted-reg operands were treated as predictable in ARMv7 Thumb; and it enables the tests for invalid and unpredictable instructions to run on both ARMv7 and ARMv8. Reviewers: jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D14141 llvm-svn: 251516		2015-10-28 13:58:36 +00:00
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AArch64	[MC layer][AArch64] llvm-mc accepts 4-bit immediate values for	2015-10-05 13:42:31 +00:00
ARM	[ARM] Allow SP in rGPR, starting from ARMv8	2015-10-28 13:58:36 +00:00
Hexagon	[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.	2015-06-10 16:52:32 +00:00
Mips	[mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions	2015-10-28 11:04:29 +00:00
PowerPC	[PowerPC] Replace cntlz[.] with cntlzw[.]	2015-10-28 03:26:45 +00:00
Sparc	[Sparc] Implement i64 load/store support for 32-bit sparc.	2015-08-10 19:11:39 +00:00
SystemZ	[SystemZ] Add assembly instructions for obtaining clock values as well as CPU features	2015-10-01 14:43:48 +00:00
X86	[llvm-mc] Ignore opcode size prefix in 64-bit CALL disassembly	2015-08-26 16:20:29 +00:00
XCore	Reduce verbiage of lit.local.cfg files	2014-06-09 22:42:55 +00:00