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llvm-project/llvm/test/CodeGen
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Stanislav Mekhanoshin 0a11829ab2 Allow machine dce to remove uses in the same instruction 
Machine DCE cannot remove a dead definition if there are non-dbg uses.
A use however can be in the same instruction:

  dead %0 = INST %0

Such instructions sometimes created by Detect dead lanes pass.

Allow this instruction to be deleted despite the use if the only use
belongs to the same instruction.

Differential Revision: https://reviews.llvm.org/D59565

llvm-svn: 356619
 		2019-03-20 21:42:05 +00:00
..
AArch64 [AArch64][GlobalISel] Add an optimization to select vector DUP instructions. 2019-03-19 21:43:05 +00:00
AMDGPU Allow machine dce to remove uses in the same instruction 2019-03-20 21:42:05 +00:00
ARC [ARC] Add ARCOptAddrMode pass to generate postincrement loads/stores. 2019-03-20 20:06:21 +00:00
ARM [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1. 2019-03-20 19:40:45 +00:00
AVR [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. 2019-03-13 17:07:09 +00:00
BPF [BPF] Add BTF Var and DataSec Support 2019-03-16 15:36:31 +00:00
Generic [AVR] Remove unneeded XFAILs from the Generic CodeGen tests 2019-01-20 11:16:58 +00:00
Hexagon [Hexagon] Remove icmp undef from reduced tests 2019-03-15 15:07:44 +00:00
Inputs
…
Lanai
…
MIR MIR: Allow targets to serialize MachineFunctionInfo 2019-03-14 22:54:43 +00:00
MSP430 [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. 2019-03-13 17:07:09 +00:00
Mips RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
NVPTX [Codegen] fix typos in test case 2019-03-02 08:03:59 +00:00
PowerPC RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
RISCV [RISCV] Extend test/CodeGen/RISCV/callee-saved-* to test getCalleePreservedRegs 2019-03-14 08:17:44 +00:00
SPARC [SPARC] Regenerate label test for D59363 2019-03-15 11:24:17 +00:00
SystemZ RegAllocFast: Remove early selection loop, the spill calculation will report cost 0 anyway for free regs 2019-03-19 19:01:34 +00:00
Thumb [ARM] Eliminate redundant "mov rN, sp" instructions in Thumb1. 2019-03-20 19:40:45 +00:00
Thumb2 [ARM] Check that CPSR does not have other uses 2019-03-17 21:36:15 +00:00
WebAssembly [WebAssembly] Target features section 2019-03-20 20:26:45 +00:00
WinCFGuard
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WinEH Fix invalid target triples in tests. (NFC) 2019-03-04 23:37:41 +00:00
X86 [X86] Call lowerShuffleAsBitMask for 512-bit vectors in lowerShuffleAsBlend. 2019-03-20 21:30:20 +00:00
XCore [DAGCombiner] If a TokenFactor would be merged into its user, consider the user later. 2019-03-13 17:07:09 +00:00