forked from OSchip/llvm-project
321 lines
6.7 KiB
ArmAsm
321 lines
6.7 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple=mipsel-unknown-nacl %s \
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# RUN: | llvm-objdump -triple mipsel -disassemble -no-show-raw-insn - \
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# RUN: | FileCheck %s
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# This test tests that address-masking sandboxing is added when given assembly
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# input.
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# Test that address-masking sandboxing is added before indirect branches and
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# returns.
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.align 4
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test1:
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.set noreorder
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jr $a0
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nop
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jr $ra
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nop
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# CHECK-LABEL: test1:
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# CHECK: and $4, $4, $14
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# CHECK-NEXT: jr $4
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# Check that additional nop is inserted, to align mask and jr to the next
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# bundle.
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK: and $ra, $ra, $14
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# CHECK-NEXT: jr $ra
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# Test that address-masking sandboxing is added before load instructions.
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.align 4
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test2:
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.set noreorder
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lb $4, 0($1)
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nop
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lbu $4, 0($2)
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lh $4, 0($3)
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lhu $1, 0($4)
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lw $4, 0($5)
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lwc1 $f0, 0($6)
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ldc1 $f2, 0($7)
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ll $4, 0($8)
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lwl $4, 0($9)
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lwr $4, 0($10)
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lw $4, 0($sp)
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lw $4, 0($t8)
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# CHECK-LABEL: test2:
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# CHECK: and $1, $1, $15
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# CHECK-NEXT: lb $4, 0($1)
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# Check that additional nop is inserted, to align mask and load to the next
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# bundle.
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# CHECK: nop
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# CHECK: nop
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# CHECK: and $2, $2, $15
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# CHECK-NEXT: lbu $4, 0($2)
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# CHECK: and $3, $3, $15
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# CHECK-NEXT: lh $4, 0($3)
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# CHECK: and $4, $4, $15
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# CHECK-NEXT: lhu $1, 0($4)
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# CHECK: and $5, $5, $15
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# CHECK-NEXT: lw $4, 0($5)
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# CHECK: and $6, $6, $15
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# CHECK-NEXT: lwc1 $f0, 0($6)
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# CHECK: and $7, $7, $15
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# CHECK-NEXT: ldc1 $f2, 0($7)
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# CHECK: and $8, $8, $15
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# CHECK-NEXT: ll $4, 0($8)
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# CHECK: and $9, $9, $15
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# CHECK-NEXT: lwl $4, 0($9)
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# CHECK: and $10, $10, $15
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# CHECK-NEXT: lwr $4, 0($10)
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# Check that loads where base register is $sp or $t8 (thread pointer register)
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# are not masked.
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# CHECK-NOT: and
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# CHECK: lw $4, 0($sp)
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# CHECK-NOT: and
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# CHECK: lw $4, 0($24)
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# Test that address-masking sandboxing is added before store instructions.
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.align 4
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test3:
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.set noreorder
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sb $4, 0($1)
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nop
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sh $4, 0($2)
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sw $4, 0($3)
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swc1 $f0, 0($4)
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sdc1 $f2, 0($5)
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swl $4, 0($6)
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swr $4, 0($7)
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sc $4, 0($8)
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sw $4, 0($sp)
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sw $4, 0($t8)
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# CHECK-LABEL: test3:
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# CHECK: and $1, $1, $15
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# CHECK-NEXT: sb $4, 0($1)
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# Check that additional nop is inserted, to align mask and store to the next
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# bundle.
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# CHECK: nop
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# CHECK: nop
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# CHECK: and $2, $2, $15
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# CHECK-NEXT: sh $4, 0($2)
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# CHECK: and $3, $3, $15
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# CHECK-NEXT: sw $4, 0($3)
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# CHECK: and $4, $4, $15
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# CHECK-NEXT: swc1 $f0, 0($4)
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# CHECK: and $5, $5, $15
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# CHECK-NEXT: sdc1 $f2, 0($5)
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# CHECK: and $6, $6, $15
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# CHECK-NEXT: swl $4, 0($6)
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# CHECK: and $7, $7, $15
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# CHECK-NEXT: swr $4, 0($7)
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# CHECK: and $8, $8, $15
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# CHECK-NEXT: sc $4, 0($8)
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# Check that stores where base register is $sp or $t8 (thread pointer register)
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# are not masked.
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# CHECK-NOT: and
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# CHECK: sw $4, 0($sp)
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# CHECK-NOT: and
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# CHECK: sw $4, 0($24)
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# Test that address-masking sandboxing is added after instructions that change
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# stack pointer.
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.align 4
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test4:
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.set noreorder
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addiu $sp, $sp, 24
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nop
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addu $sp, $sp, $1
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lw $sp, 0($2)
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lw $sp, 123($sp)
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sw $sp, 123($sp)
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# CHECK-LABEL: test4:
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# CHECK: addiu $sp, $sp, 24
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# CHECK-NEXT: and $sp, $sp, $15
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# Check that additional nop is inserted, to align instruction and mask to the
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# next bundle.
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# CHECK: nop
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# CHECK: nop
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# CHECK: addu $sp, $sp, $1
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# CHECK-NEXT: and $sp, $sp, $15
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# Since we next check sandboxing sequence which consists of 3 instructions,
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# check that 2 additional nops are inserted, to align it to the next bundle.
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# CHECK: nop
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# CHECK: nop
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# Check that for instructions that change stack-pointer and load from memory
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# masks are added before and after the instruction.
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# CHECK: and $2, $2, $15
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# CHECK-NEXT: lw $sp, 0($2)
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# CHECK-NEXT: and $sp, $sp, $15
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# For loads where $sp is destination and base, check that mask is added after
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# but not before.
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# CHECK-NOT: and
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# CHECK: lw $sp, 123($sp)
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# CHECK-NEXT: and $sp, $sp, $15
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# For stores where $sp is destination and base, check that mask is added neither
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# before nor after.
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# CHECK-NOT: and
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# CHECK: sw $sp, 123($sp)
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# CHECK-NOT: and
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# Test that call + branch delay is aligned at bundle end. Test that mask is
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# added before indirect calls.
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.align 4
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test5:
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.set noreorder
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jal func1
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addiu $4, $zero, 1
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nop
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bal func2
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addiu $4, $zero, 2
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nop
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nop
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bltzal $t1, func3
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addiu $4, $zero, 3
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nop
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nop
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nop
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bgezal $t2, func4
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addiu $4, $zero, 4
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jalr $t9
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addiu $4, $zero, 5
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# CHECK: nop
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# CHECK-NEXT: nop
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# CHECK-LABEL: test5:
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# CHECK-NEXT: jal
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# CHECK-NEXT: addiu $4, $zero, 1
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: bal
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# CHECK-NEXT: addiu $4, $zero, 2
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: bltzal
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# CHECK-NEXT: addiu $4, $zero, 3
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: bgezal
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# CHECK-NEXT: addiu $4, $zero, 4
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# CHECK-NEXT: nop
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# CHECK-NEXT: and $25, $25, $14
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# CHECK-NEXT: jalr $25
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# CHECK-NEXT: addiu $4, $zero, 5
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# Test that we can put non-dangerous loads and stores in branch delay slot.
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.align 4
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test6:
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.set noreorder
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jal func1
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sw $4, 0($sp)
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bal func2
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lw $5, 0($t8)
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jalr $t9
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sw $sp, 0($sp)
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# CHECK: nop
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# CHECK-NEXT: nop
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# CHECK-LABEL: test6:
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# CHECK-NEXT: jal
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# CHECK-NEXT: sw $4, 0($sp)
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# CHECK-NEXT: nop
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# CHECK-NEXT: nop
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# CHECK-NEXT: bal
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# CHECK-NEXT: lw $5, 0($24)
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# CHECK-NEXT: nop
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# CHECK-NEXT: and $25, $25, $14
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# CHECK-NEXT: jalr
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# CHECK-NEXT: sw $sp, 0($sp)
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