forked from OSchip/llvm-project
1b57c7a0f4
Summary: Fixed setting predicates for compressed instructions. Some instructions were being generated with C extension enabled only, without proper checks for the other required extensions like F, D and 32 and 64-bit target checks. Affected instructions: C_FLD, C_FLW, C_LD, C_FSD, C_FSW, C_SD, C_JAL, C_ADDIW, C_SUBW, C_ADDW, C_FLDSP, C_FLWSP, C_LDSP, C_FSDSP, C_FSWSP, C_SDSP Reviewers: asb, shiva0217 Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, llvm-commits Differential Revision: https://reviews.llvm.org/D42132 llvm-svn: 322876 |
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.. | ||
AsmParser | ||
Disassembler | ||
InstPrinter | ||
MCTargetDesc | ||
TargetInfo | ||
CMakeLists.txt | ||
LLVMBuild.txt | ||
RISCV.h | ||
RISCV.td | ||
RISCVAsmPrinter.cpp | ||
RISCVCallingConv.td | ||
RISCVFrameLowering.cpp | ||
RISCVFrameLowering.h | ||
RISCVISelDAGToDAG.cpp | ||
RISCVISelLowering.cpp | ||
RISCVISelLowering.h | ||
RISCVInstrFormats.td | ||
RISCVInstrFormatsC.td | ||
RISCVInstrInfo.cpp | ||
RISCVInstrInfo.h | ||
RISCVInstrInfo.td | ||
RISCVInstrInfoA.td | ||
RISCVInstrInfoC.td | ||
RISCVInstrInfoD.td | ||
RISCVInstrInfoF.td | ||
RISCVInstrInfoM.td | ||
RISCVMCInstLower.cpp | ||
RISCVMachineFunctionInfo.h | ||
RISCVRegisterInfo.cpp | ||
RISCVRegisterInfo.h | ||
RISCVRegisterInfo.td | ||
RISCVSubtarget.cpp | ||
RISCVSubtarget.h | ||
RISCVTargetMachine.cpp | ||
RISCVTargetMachine.h |