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Thomas Lively a3f974f3c3 [WebAssembly] SIMD bitmask intrinsics and builtin functions 
Summary:
These experimental new instructions are proposed in
https://github.com/WebAssembly/simd/pull/201.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D76397
 		2020-03-19 17:15:37 -07:00
..
AArch64 [GlobalISel] Port some basic shufflevector undef combines from the DAGCombiner 2020-03-19 16:46:06 -07:00
AMDGPU [AMDGPU] Move frame pointer from s34 to s33 2020-03-19 15:35:16 -04:00
ARC
…
ARM [NFC][ARM] Fix for buildbots 2020-03-19 15:50:13 +00:00
AVR [AVR] Fix incorrect register state for LDRdPtr 2020-03-03 17:34:54 +08:00
BPF [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
Generic [NFC] Add missing REQUIRES clause to a test 2020-03-18 16:35:10 +03:00
Hexagon [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
Inputs
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Lanai Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`""" 2020-02-13 10:16:06 -08:00
MIR [AMDGPU] Move frame pointer from s34 to s33 2020-03-19 15:35:16 -04:00
MSP430
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Mips [GlobalISel] combine G_TRUNC with G_MERGE_VALUES 2020-03-16 14:42:01 +01:00
NVPTX ARM: Fixup some tests using denormal-fp-math attribute 2020-03-10 14:02:06 -04:00
PowerPC [PowerPC][AIX] Simplify the check prefixes in the ByVal lit tests. [NFC] 2020-03-19 10:59:48 -04:00
RISCV [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
SPARC [Sparc] Fix incorrect operand for matching CMPri pattern 2020-03-02 11:36:32 +08:00
SystemZ [TargetLowering] Only demand a rotation's modulo amount bits 2020-03-17 21:23:46 +00:00
Thumb [test] llvm/test/: change llvm-objdump single-dash long options to double-dash options 2020-03-15 17:46:23 -07:00
Thumb2 [ARM,MVE] Add intrinsics for the VQDMLAD family. 2020-03-18 17:11:22 +00:00
VE [VE] Target-specific bit size for sjljehprepare 2020-03-10 17:51:16 +01:00
WebAssembly [WebAssembly] SIMD bitmask intrinsics and builtin functions 2020-03-19 17:15:37 -07:00
WinCFGuard
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WinEH
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X86 Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
XCore [XCore] Add instruction pattern for bitrev 2020-02-21 09:28:49 +08:00