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llvm-project/llvm/test/CodeGen
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Craig Topper 63157c4784 [X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round intrinsics. 
The VRNDSCALE instructions implement a superset of the (V)ROUND instructions. They are equivalent if the upper 4-bits of the immediate are 0.

This patch lowers the legacy intrinsics to the VRNDSCALE ISD node and masks the upper bits of the immediate to 0. This allows us to take advantage of the larger register encoding space.

We should maybe consider converting VRNDSCALE back to VROUND in the EVEX to VEX pass if the extended registers are not being used.

I notice some load folding opportunities being missed for the VRNDSCALESS/SD instructions that I'll try to fix in future patches.

llvm-svn: 318008
 		2017-11-13 02:03:00 +00:00
..
AArch64 Fix some misc. -enable-var-scope violations 2017-11-13 01:47:52 +00:00
AMDGPU AMDGPU: Select d16 loads into low component of register 2017-11-13 00:22:09 +00:00
ARC
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ARM [GlobalISel] Enable legalizing non-power-of-2 sized types. 2017-11-07 10:34:34 +00:00
AVR [AVR] Fix the select-mbb-placement-bug.ll 2017-10-20 04:17:14 +00:00
BPF bpf: fix bug on silently truncating 64-bit immediate 2017-10-16 04:14:53 +00:00
Generic Add an @llvm.sideeffect intrinsic 2017-11-08 21:59:51 +00:00
Hexagon [Hexagon] Prefer L2_loadrub_io over L4_loadrub_rr 2017-11-02 21:56:59 +00:00
Inputs
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Lanai MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
MIR [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
MSP430
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Mips [mips] Correct microMIP's jump and add unconditional branch pseudo 2017-11-09 16:02:18 +00:00
NVPTX [NVPTX] Implement __nvvm_atom_add_gen_d builtin. 2017-11-07 22:10:54 +00:00
Nios2
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PowerPC Use new vector insert half-word and byte instructions when we see insertelement on '8 x i16' and '16 x i8' types. Also extended existing lit testcase to cover these cases. 2017-11-07 20:55:43 +00:00
RISCV [RISCV] Re-generate test/CodeGen/RISCV/alu32.ll using update_llc_test_checks.py 2017-11-09 15:45:42 +00:00
SPARC Revert "Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"" 2017-10-03 16:59:13 +00:00
SystemZ [RegAlloc, SystemZ] Increase number of LOCRs by passing "hard" regalloc hints. 2017-11-10 08:46:26 +00:00
Thumb [ARM] Dynamic stack alignment for 16-bit Thumb 2017-10-22 11:56:35 +00:00
Thumb2 [ARM] Honor -mfloat-abi for libcall calling convention 2017-10-26 21:42:32 +00:00
WebAssembly [WebAssembly] Fix stack offsets of return values from call lowering. 2017-11-10 16:26:04 +00:00
WinEH Make x86 __ehhandler comdat if parent function is 2017-10-20 17:04:43 +00:00
X86 [X86] Use EVEX encoded VRNDSCALE instructions to implement the legacy round intrinsics. 2017-11-13 02:03:00 +00:00
XCore [MC] Suppress .Lcfi labels when emitting textual assembly 2017-10-10 00:57:36 +00:00