forked from OSchip/llvm-project
78 lines
3.1 KiB
LLVM
78 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
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; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
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; Test reduce scalarization in fpext v2f32 to v2f64 from the extract_subvector v4f32 node.
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define dso_local void @test(<4 x float>* nocapture readonly %a, <2 x double>* nocapture %b, <2 x double>* nocapture %c) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv vs0, 0(r3)
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; CHECK-NEXT: xxmrglw vs1, vs0, vs0
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; CHECK-NEXT: xxmrghw vs0, vs0, vs0
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; CHECK-NEXT: xvcvspdp vs1, vs1
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; CHECK-NEXT: xvcvspdp vs0, vs0
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; CHECK-NEXT: stxv vs1, 0(r4)
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; CHECK-NEXT: stxv vs0, 0(r5)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxv vs0, 0(r3)
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; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0
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; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0
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; CHECK-BE-NEXT: xvcvspdp vs1, vs1
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; CHECK-BE-NEXT: xvcvspdp vs0, vs0
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; CHECK-BE-NEXT: stxv vs1, 0(r4)
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; CHECK-BE-NEXT: stxv vs0, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <4 x float>, <4 x float>* %a, align 16
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%shuffle = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 0, i32 1>
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%shuffle1 = shufflevector <4 x float> %0, <4 x float> undef, <2 x i32> <i32 2, i32 3>
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%vecinit4 = fpext <2 x float> %shuffle to <2 x double>
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%vecinit11 = fpext <2 x float> %shuffle1 to <2 x double>
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store <2 x double> %vecinit4, <2 x double>* %b, align 16
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store <2 x double> %vecinit11, <2 x double>* %c, align 16
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ret void
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}
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; Ensure we don't crash for wider types
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define dso_local void @test2(<16 x float>* nocapture readonly %a, <2 x double>* nocapture %b, <2 x double>* nocapture %c) {
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; CHECK-LABEL: test2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv vs0, 0(r3)
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; CHECK-NEXT: xxmrglw vs1, vs0, vs0
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; CHECK-NEXT: xxmrghw vs0, vs0, vs0
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; CHECK-NEXT: xvcvspdp vs1, vs1
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; CHECK-NEXT: xvcvspdp vs0, vs0
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; CHECK-NEXT: stxv vs1, 0(r4)
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; CHECK-NEXT: stxv vs0, 0(r5)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: test2:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxv vs0, 0(r3)
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; CHECK-BE-NEXT: xxmrghw vs1, vs0, vs0
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; CHECK-BE-NEXT: xxmrglw vs0, vs0, vs0
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; CHECK-BE-NEXT: xvcvspdp vs1, vs1
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; CHECK-BE-NEXT: xvcvspdp vs0, vs0
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; CHECK-BE-NEXT: stxv vs1, 0(r4)
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; CHECK-BE-NEXT: stxv vs0, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <16 x float>, <16 x float>* %a, align 16
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%shuffle = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 0, i32 1>
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%shuffle1 = shufflevector <16 x float> %0, <16 x float> undef, <2 x i32> <i32 2, i32 3>
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%vecinit4 = fpext <2 x float> %shuffle to <2 x double>
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%vecinit11 = fpext <2 x float> %shuffle1 to <2 x double>
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store <2 x double> %vecinit4, <2 x double>* %b, align 16
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store <2 x double> %vecinit11, <2 x double>* %c, align 16
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ret void
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}
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