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llvm-project/llvm/test/CodeGen/X86/GlobalISel
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Francis Visoiu Mistrih 25528d6de7 [CodeGen] Unify MBB reference format in both MIR and debug output 
As part of the unification of the debug format and the MIR format, print
MBB references as '%bb.5'.

The MIR printer prints the IR name of a MBB only for block definitions.

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g'
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g'
* find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g'
* grep -nr 'BB#' and fix

Differential Revision: https://reviews.llvm.org/D40422

llvm-svn: 319665
 		2017-12-04 17:18:51 +00:00
..
GV.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
add-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
add-vec.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
and-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
binop.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
br.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
brcond.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
callingconv.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
cmp.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
constant.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ext-x86-64.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
ext.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fadd-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fconstant.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fdiv-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fmul-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fpext-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
frameIndex.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
fsub-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
gep.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
irtranslator-callingconv.ll Control-Flow Enforcement Technology - Shadow Stack support (LLVM side) 2017-11-26 13:02:45 +00:00
legalize-GV.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-add-v128.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-add-v256.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-add-v512.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-add.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-and-scalar.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-brcond.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-cmp.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-constant.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-ext-x86-64.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-ext.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-fadd-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-fdiv-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-fmul-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-fpext-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-fsub-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-gep.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-insert-vec256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-insert-vec512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-memop-scalar.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-mul-scalar.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-mul-v128.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-mul-v256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-mul-v512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
legalize-or-scalar.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-phi.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
legalize-sub-v128.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-sub-v256.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-sub-v512.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-sub.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-trunc.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-undef.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
legalize-xor-scalar.mir [GISel]: Rework legalization algorithm for better elimination of 2017-11-14 22:42:19 +00:00
lit.local.cfg
…
memop-scalar-x32.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
memop-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
memop-vec.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mul-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
mul-vec.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
or-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
phi.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
regbankselect-AVX2.mir [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. 2017-06-06 08:16:19 +00:00
regbankselect-AVX512.mir [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. 2017-06-06 08:16:19 +00:00
regbankselect-X32.mir [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. 2017-06-06 08:16:19 +00:00
regbankselect-X86_64.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
select-GV.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-add-v128.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-add-v256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-add-v512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-add-x32.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-add.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-and-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-blsi.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-blsr.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-br.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
select-brcond.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
select-cmp.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-constant.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-copy.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-ext-x86-64.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-ext.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-extract-vec256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-extract-vec512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-fadd-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-fconstant.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-fdiv-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-fmul-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-fpext-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-frameIndex.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-fsub-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-gep.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-inc.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-insert-vec256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-insert-vec512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-intrinsic-x86-flags-read-u32.mir [MIRPrinter] Use %subreg.xxx syntax for subregister index operands 2017-11-06 21:46:06 +00:00
select-leaf-constant.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-memop-scalar-x32.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-memop-scalar.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-memop-v128.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-memop-v256.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-memop-v512.mir [CodeGen] Always use `printReg` to print registers in both MIR and debug 2017-11-30 16:12:24 +00:00
select-merge-vec256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-merge-vec512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-mul-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-mul-vec.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-or-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-phi.mir [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
select-sub-v128.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-sub-v256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-sub-v512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-sub.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-trunc.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-undef.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-unmerge-vec256.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-unmerge-vec512.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
select-xor-scalar.mir MIR: Print the register class or bank in vreg defs 2017-10-24 18:04:54 +00:00
sub-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
sub-vec.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
trunc.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
undef.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
x86_64-fallback.ll [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output 2017-11-30 12:12:19 +00:00
xor-scalar.ll [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00