forked from OSchip/llvm-project
6207a4dadc
The trouble as in ARMAsmParser, in ParseInstruction method. It assumes that ARM::R12 + 1 == ARM::SP. It is wrong, since ARM::<Register> codes are generated by tablegen and actually could be any random numbers. llvm-svn: 205524 |
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Analysis | ||
Assembler | ||
Bindings | ||
Bitcode | ||
BugPoint | ||
CodeGen | ||
DebugInfo | ||
ExecutionEngine | ||
Feature | ||
FileCheck | ||
Instrumentation | ||
Integer | ||
JitListener | ||
LTO | ||
Linker | ||
MC | ||
Object | ||
Other | ||
TableGen | ||
Transforms | ||
Unit | ||
Verifier | ||
YAMLParser | ||
tools | ||
.clang-format | ||
CMakeLists.txt | ||
Makefile | ||
Makefile.tests | ||
TestRunner.sh | ||
lit.cfg | ||
lit.site.cfg.in |