Andrea Di Biagio beb5213a2e [MCA][InstrBuilder] Check for the presence of flag VariadicOpsAreDefs. ... This patch fixes the logic that checks for variadic register definitions, Before llvm-svn 348114 (commit 4cf35b4ab0), it was not possible to explicitly mark variadic operands as definitions. By default, variadic operands of an MCInst were always assumed to be uses. A number of had-hoc checks were introduced in the InstrBuilder to fix the processing of variadic register operands of ARM ldm/stm variants. This patch simply replaces those old (and buggy) checks with a much simpler (and correct) check for MCID::Flag::VariadicOpsAreDefs.		2021-06-15 09:52:38 +01:00
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cortex-a57-basic-instructions.s	Add support for branch forms of ALU instructions to Cortex-A57 model	2020-11-24 11:43:51 +03:00
cortex-a57-carryover.s	[MCA][InstrBuilder] Check for the presence of flag VariadicOpsAreDefs.	2021-06-15 09:52:38 +01:00
cortex-a57-memory-instructions.s	…
cortex-a57-neon-instructions.s	…
cortex-a57-thumb.s	[llvm-mca] Fix processing thumb instruction set	2020-11-24 18:27:59 +03:00
lit.local.cfg	…
m4-int.s	…
m4-targetfeatures.s	…
m7-fp.s	[ARM] Use ProcResGroup in Cortex-M7 scheduling model	2021-04-19 21:23:05 +01:00
m7-int.s	[ARM] Use ProcResGroup in Cortex-M7 scheduling model	2021-04-19 21:23:05 +01:00
m7-negative-readadvance.s	[ARM] Use ProcResGroup in Cortex-M7 scheduling model	2021-04-19 21:23:05 +01:00
memcpy-ldm-stm.s	…
simple-cortex-m33.s	…
simple-test-cortex-a9.s	…
unsupported-write-variant.s	…
vld1-index-update.s	…