forked from OSchip/llvm-project
206 lines
7.4 KiB
ArmAsm
206 lines
7.4 KiB
ArmAsm
@ RUN: not llvm-mc -triple=thumbv7-unknown-linux-gnueabi -arm-implicit-it=thumb -show-encoding < %s 2>&1 | FileCheck %s
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.syntax unified
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@ Note: The error stream for XFAIL needs to get checked first.
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ldr.w r1, [r1, #-4]!
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ldr.w r1, [r0, #256]!
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ldr.w r1, [r0, #-256]!
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ldr.w r1, [pc, #-4]!
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ldr.w r1, [r1], #4
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ldr.w r0, [r0], #4
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ldr.w r0, [r1], #256
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ldr.w r0, [r1], #-256
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str.w r0, [r0, #-4]!
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str.w pc, [r0, #-4]!
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str.w r1, [pc, #-4]!
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str.w r1, [r2, #256]!
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str.w r1, [r2, #-256]!
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str.w r0, [r0], #4
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str.w pc, [r0], #4
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str.w r1, [r0], #256
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str.w r1, [r0], #-256
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@@ XFAIL
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@ CHECK: error: destination register and base register can't be identical
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@ CHECK-NEXT: ldr.w r1, [r1, #-4]!
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK-NEXT: ldr.w r1, [r0, #256]!
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@ CHECK: note: invalid operand for instruction
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@ CHECK: note: too many operands for instruction
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@ CHECK: error: invalid operand for instruction
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@ CHECK-NEXT: ldr.w r1, [r0, #-256]!
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK-NEXT: ldr.w r1, [pc, #-4]!
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@ CHECK: note: invalid operand for instruction
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@ CHECK: note: too many operands for instruction
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@ CHECK: error: destination register and base register can't be identical
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@ CHECK-NEXT: ldr.w r1, [r1], #4
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@ CHECK: error: destination register and base register can't be identical
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@ CHECK-NEXT: ldr.w r0, [r0], #4
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@ CHECK: error: operand must be in range [-255, 255]
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@ CHECK-NEXT: ldr.w r0, [r1], #256
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@ CHECK: error: operand must be in range [-255, 255]
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@ CHECK-NEXT: ldr.w r0, [r1], #-256
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@ CHECK: error: destination register and base register can't be identical
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@ CHECK-NEXT: str.w r0, [r0, #-4]!
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@ CHECK: error: operand must be a register in range [r0, r14]
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@ CHECK-NEXT: str.w pc, [r0, #-4]!
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@ CHECK: error: invalid operand for instruction
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@ CHECK-NEXT: str.w r1, [pc, #-4]!
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK-NEXT: str.w r1, [r2, #256]!
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@ CHECK: note: invalid operand for instruction
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@ CHECK: note: too many operands for instruction
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@ CHECK: error: invalid operand for instruction
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@ CHECK-NEXT: str.w r1, [r2, #-256]!
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@ CHECK: error: destination register and base register can't be identical
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@ CHECK-NEXT: str.w r0, [r0], #4
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@ CHECK: error: operand must be a register in range [r0, r14]
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@ CHECK-NEXT: str.w pc, [r0], #4
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@ CHECK: error: operand must be in range [-255, 255]
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@ CHECK-NEXT: str.w r1, [r0], #256
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@ CHECK: error: operand must be in range [-255, 255]
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@ CHECK-NEXT: str.w r1, [r0], #-256
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@@ XPASS
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@ Simple checks that we get the same encoding w/ and w/o the .w suffix.
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ldr r3, [r1], #4
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ldr.w r3, [r1], #4
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str r3, [r0], #4
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str.w r3, [r0], #4
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ldr r3, [r1, #-4]!
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ldr.w r3, [r1, #-4]!
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str r3, [r0, #-4]!
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str.w r3, [r0, #-4]!
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@ CHECK: ldr r3, [r1], #4 @ encoding: [0x51,0xf8,0x04,0x3b]
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@ CHECK: ldr r3, [r1], #4 @ encoding: [0x51,0xf8,0x04,0x3b]
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@ CHECK: str r3, [r0], #4 @ encoding: [0x40,0xf8,0x04,0x3b]
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@ CHECK: str r3, [r0], #4 @ encoding: [0x40,0xf8,0x04,0x3b]
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@ CHECK: ldr r3, [r1, #-4]! @ encoding: [0x51,0xf8,0x04,0x3d]
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@ CHECK: ldr r3, [r1, #-4]! @ encoding: [0x51,0xf8,0x04,0x3d]
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@ CHECK: str r3, [r0, #-4]! @ encoding: [0x40,0xf8,0x04,0x3d]
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@ CHECK: str r3, [r0, #-4]! @ encoding: [0x40,0xf8,0x04,0x3d]
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@@ LDR pre-increment w/ writeback
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@ Vary Rt.
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ldr.w r0, [r1, #-4]!
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ldr.w sp, [r1, #-4]! @ TODO: GAS warns for this
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ldr.w pc, [r1, #-4]!
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@ Vary Rn.
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ldr.w r1, [r0, #-4]!
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ldr.w r1, [sp, #-4]!
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@ Vary imm.
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ldr.w r1, [r0, #255]!
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ldr.w r1, [r0, #-255]!
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ldr.w r1, [r0, #0]!
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@ Condition codes.
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ldreq.w r1, [r0, #255]!
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ldrle.w r1, [r0, #255]!
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@ CHECK: ldr r0, [r1, #-4]! @ encoding: [0x51,0xf8,0x04,0x0d]
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@ CHECK: ldr sp, [r1, #-4]! @ encoding: [0x51,0xf8,0x04,0xdd]
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@ CHECK: ldr pc, [r1, #-4]! @ encoding: [0x51,0xf8,0x04,0xfd]
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@ CHECK: ldr r1, [r0, #-4]! @ encoding: [0x50,0xf8,0x04,0x1d]
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@ CHECK: ldr r1, [sp, #-4]! @ encoding: [0x5d,0xf8,0x04,0x1d]
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@ CHECK: ldr r1, [r0, #255]! @ encoding: [0x50,0xf8,0xff,0x1f]
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@ CHECK: ldr r1, [r0, #-255]! @ encoding: [0x50,0xf8,0xff,0x1d]
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@ CHECK: ldr r1, [r0, #0]! @ encoding: [0x50,0xf8,0x00,0x1f]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: ldreq r1, [r0, #255]! @ encoding: [0x50,0xf8,0xff,0x1f]
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@ CHECK: it le @ encoding: [0xd8,0xbf]
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@ CHECK: ldrle r1, [r0, #255]! @ encoding: [0x50,0xf8,0xff,0x1f]
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@@ LDR post-increment
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@ Vary Rt.
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ldr.w r0, [r1], #4
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ldr.w sp, [r1], #4 @ TODO: GAS warns for this
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ldr.w pc, [r1], #4
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@ Vary Rn.
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ldr.w r0, [r1], #4
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ldr.w r0, [sp], #4
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ldr.w r0, [pc], #4 @ TODO: GAS warns for this
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@ Vary imm.
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ldr.w r0, [r1], #255
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ldr.w r0, [r1], #0
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ldr.w r0, [r1], #-255
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@ Condition codes.
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ldreq.w r0, [r1], #255
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ldrle.w r0, [r1], #255
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@ CHECK: ldr r0, [r1], #4 @ encoding: [0x51,0xf8,0x04,0x0b]
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@ CHECK: ldr sp, [r1], #4 @ encoding: [0x51,0xf8,0x04,0xdb]
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@ CHECK: ldr pc, [r1], #4 @ encoding: [0x51,0xf8,0x04,0xfb]
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@ CHECK: ldr r0, [r1], #4 @ encoding: [0x51,0xf8,0x04,0x0b]
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@ CHECK: ldr r0, [sp], #4 @ encoding: [0x5d,0xf8,0x04,0x0b]
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@ CHECK: ldr r0, [pc], #4 @ encoding: [0x5f,0xf8,0x04,0x0b]
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@ CHECK: ldr r0, [r1], #255 @ encoding: [0x51,0xf8,0xff,0x0b]
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@ CHECK: ldr r0, [r1], #0 @ encoding: [0x51,0xf8,0x00,0x0b]
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@ CHECK: ldr r0, [r1], #-255 @ encoding: [0x51,0xf8,0xff,0x09]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: ldreq r0, [r1], #255 @ encoding: [0x51,0xf8,0xff,0x0b]
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@ CHECK: it le @ encoding: [0xd8,0xbf]
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@ CHECK: ldrle r0, [r1], #255 @ encoding: [0x51,0xf8,0xff,0x0b]
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@@ STR pre-increment w/ writeback
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@ Vary Rt.
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str.w r1, [r0, #-4]!
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str.w sp, [r0, #-4]!
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@ Vary Rn.
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str.w r1, [r2, #-4]!
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str.w r1, [sp, #-4]!
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@ Vary imm.
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str.w r1, [r2, #255]!
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str.w r1, [r2, #0]!
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str.w r1, [r2, #-255]!
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@ Condition codes.
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streq.w r1, [r2, #255]!
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strle.w r1, [r2, #255]!
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@ CHECK: str r1, [r0, #-4]! @ encoding: [0x40,0xf8,0x04,0x1d]
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@ CHECK: str sp, [r0, #-4]! @ encoding: [0x40,0xf8,0x04,0xdd]
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@ CHECK: str r1, [r2, #-4]! @ encoding: [0x42,0xf8,0x04,0x1d]
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@ CHECK: str r1, [sp, #-4]! @ encoding: [0x4d,0xf8,0x04,0x1d]
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@ CHECK: str r1, [r2, #255]! @ encoding: [0x42,0xf8,0xff,0x1f]
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@ CHECK: str r1, [r2, #0]! @ encoding: [0x42,0xf8,0x00,0x1f]
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@ CHECK: str r1, [r2, #-255]! @ encoding: [0x42,0xf8,0xff,0x1d]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: streq r1, [r2, #255]! @ encoding: [0x42,0xf8,0xff,0x1f]
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@ CHECK: it le @ encoding: [0xd8,0xbf]
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@ CHECK: strle r1, [r2, #255]! @ encoding: [0x42,0xf8,0xff,0x1f]
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@@ STR post-increment
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@ Vary Rt.
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str.w r1, [r0], #4
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str.w sp, [r0], #4
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@ Vary Rn.
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str.w r0, [r1], #4
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str.w r0, [sp], #4
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str.w r0, [pc], #4 @ TODO: GAS warns for this.
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@ Vary imm.
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str.w r1, [r0], #255
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str.w r1, [r0], #0
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str.w r1, [r0], #-255
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@ Condition codes.
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streq.w r1, [r0], #255
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strle.w r1, [r0], #255
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@ CHECK: str r1, [r0], #4 @ encoding: [0x40,0xf8,0x04,0x1b]
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@ CHECK: str sp, [r0], #4 @ encoding: [0x40,0xf8,0x04,0xdb]
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@ CHECK: str r0, [r1], #4 @ encoding: [0x41,0xf8,0x04,0x0b]
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@ CHECK: str r0, [sp], #4 @ encoding: [0x4d,0xf8,0x04,0x0b]
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@ CHECK: str r0, [pc], #4 @ encoding: [0x4f,0xf8,0x04,0x0b]
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@ CHECK: str r1, [r0], #255 @ encoding: [0x40,0xf8,0xff,0x1b]
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@ CHECK: str r1, [r0], #0 @ encoding: [0x40,0xf8,0x00,0x1b]
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@ CHECK: str r1, [r0], #-255 @ encoding: [0x40,0xf8,0xff,0x19]
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@ CHECK: it eq @ encoding: [0x08,0xbf]
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@ CHECK: streq r1, [r0], #255 @ encoding: [0x40,0xf8,0xff,0x1b]
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@ CHECK: it le @ encoding: [0xd8,0xbf]
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@ CHECK: strle r1, [r0], #255 @ encoding: [0x40,0xf8,0xff,0x1b]
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