forked from OSchip/llvm-project
693 lines
26 KiB
C++
693 lines
26 KiB
C++
//===--------------------- InstrBuilder.cpp ---------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements the InstrBuilder interface.
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///
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//===----------------------------------------------------------------------===//
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#include "llvm/MCA/InstrBuilder.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/WithColor.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "llvm-mca"
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namespace llvm {
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namespace mca {
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InstrBuilder::InstrBuilder(const llvm::MCSubtargetInfo &sti,
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const llvm::MCInstrInfo &mcii,
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const llvm::MCRegisterInfo &mri,
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const llvm::MCInstrAnalysis *mcia)
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: STI(sti), MCII(mcii), MRI(mri), MCIA(mcia), FirstCallInst(true),
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FirstReturnInst(true) {
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computeProcResourceMasks(STI.getSchedModel(), ProcResourceMasks);
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}
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static void initializeUsedResources(InstrDesc &ID,
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const MCSchedClassDesc &SCDesc,
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const MCSubtargetInfo &STI,
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ArrayRef<uint64_t> ProcResourceMasks) {
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const MCSchedModel &SM = STI.getSchedModel();
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// Populate resources consumed.
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using ResourcePlusCycles = std::pair<uint64_t, ResourceUsage>;
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std::vector<ResourcePlusCycles> Worklist;
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// Track cycles contributed by resources that are in a "Super" relationship.
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// This is required if we want to correctly match the behavior of method
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// SubtargetEmitter::ExpandProcResource() in Tablegen. When computing the set
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// of "consumed" processor resources and resource cycles, the logic in
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// ExpandProcResource() doesn't update the number of resource cycles
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// contributed by a "Super" resource to a group.
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// We need to take this into account when we find that a processor resource is
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// part of a group, and it is also used as the "Super" of other resources.
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// This map stores the number of cycles contributed by sub-resources that are
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// part of a "Super" resource. The key value is the "Super" resource mask ID.
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DenseMap<uint64_t, unsigned> SuperResources;
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unsigned NumProcResources = SM.getNumProcResourceKinds();
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APInt Buffers(NumProcResources, 0);
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bool AllInOrderResources = true;
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bool AnyDispatchHazards = false;
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for (unsigned I = 0, E = SCDesc.NumWriteProcResEntries; I < E; ++I) {
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const MCWriteProcResEntry *PRE = STI.getWriteProcResBegin(&SCDesc) + I;
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const MCProcResourceDesc &PR = *SM.getProcResource(PRE->ProcResourceIdx);
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uint64_t Mask = ProcResourceMasks[PRE->ProcResourceIdx];
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if (PR.BufferSize < 0) {
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AllInOrderResources = false;
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} else {
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Buffers.setBit(PRE->ProcResourceIdx);
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AnyDispatchHazards |= (PR.BufferSize == 0);
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AllInOrderResources &= (PR.BufferSize <= 1);
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}
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CycleSegment RCy(0, PRE->Cycles, false);
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Worklist.emplace_back(ResourcePlusCycles(Mask, ResourceUsage(RCy)));
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if (PR.SuperIdx) {
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uint64_t Super = ProcResourceMasks[PR.SuperIdx];
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SuperResources[Super] += PRE->Cycles;
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}
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}
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ID.MustIssueImmediately = AllInOrderResources && AnyDispatchHazards;
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// Sort elements by mask popcount, so that we prioritize resource units over
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// resource groups, and smaller groups over larger groups.
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sort(Worklist, [](const ResourcePlusCycles &A, const ResourcePlusCycles &B) {
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unsigned popcntA = countPopulation(A.first);
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unsigned popcntB = countPopulation(B.first);
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if (popcntA < popcntB)
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return true;
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if (popcntA > popcntB)
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return false;
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return A.first < B.first;
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});
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uint64_t UsedResourceUnits = 0;
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// Remove cycles contributed by smaller resources.
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for (unsigned I = 0, E = Worklist.size(); I < E; ++I) {
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ResourcePlusCycles &A = Worklist[I];
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if (!A.second.size()) {
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A.second.NumUnits = 0;
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A.second.setReserved();
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ID.Resources.emplace_back(A);
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continue;
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}
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ID.Resources.emplace_back(A);
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uint64_t NormalizedMask = A.first;
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if (countPopulation(A.first) == 1) {
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UsedResourceUnits |= A.first;
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} else {
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// Remove the leading 1 from the resource group mask.
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NormalizedMask ^= PowerOf2Floor(NormalizedMask);
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}
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for (unsigned J = I + 1; J < E; ++J) {
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ResourcePlusCycles &B = Worklist[J];
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if ((NormalizedMask & B.first) == NormalizedMask) {
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B.second.CS.subtract(A.second.size() - SuperResources[A.first]);
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if (countPopulation(B.first) > 1)
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B.second.NumUnits++;
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}
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}
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}
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// A SchedWrite may specify a number of cycles in which a resource group
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// is reserved. For example (on target x86; cpu Haswell):
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//
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// SchedWriteRes<[HWPort0, HWPort1, HWPort01]> {
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// let ResourceCycles = [2, 2, 3];
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// }
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//
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// This means:
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// Resource units HWPort0 and HWPort1 are both used for 2cy.
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// Resource group HWPort01 is the union of HWPort0 and HWPort1.
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// Since this write touches both HWPort0 and HWPort1 for 2cy, HWPort01
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// will not be usable for 2 entire cycles from instruction issue.
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//
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// On top of those 2cy, SchedWriteRes explicitly specifies an extra latency
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// of 3 cycles for HWPort01. This tool assumes that the 3cy latency is an
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// extra delay on top of the 2 cycles latency.
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// During those extra cycles, HWPort01 is not usable by other instructions.
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for (ResourcePlusCycles &RPC : ID.Resources) {
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if (countPopulation(RPC.first) > 1 && !RPC.second.isReserved()) {
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// Remove the leading 1 from the resource group mask.
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uint64_t Mask = RPC.first ^ PowerOf2Floor(RPC.first);
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if ((Mask & UsedResourceUnits) == Mask)
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RPC.second.setReserved();
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}
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}
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// Identify extra buffers that are consumed through super resources.
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for (const std::pair<uint64_t, unsigned> &SR : SuperResources) {
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for (unsigned I = 1, E = NumProcResources; I < E; ++I) {
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const MCProcResourceDesc &PR = *SM.getProcResource(I);
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if (PR.BufferSize == -1)
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continue;
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uint64_t Mask = ProcResourceMasks[I];
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if (Mask != SR.first && ((Mask & SR.first) == SR.first))
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Buffers.setBit(I);
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}
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}
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// Now set the buffers.
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if (unsigned NumBuffers = Buffers.countPopulation()) {
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ID.Buffers.resize(NumBuffers);
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for (unsigned I = 0, E = NumProcResources; I < E && NumBuffers; ++I) {
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if (Buffers[I]) {
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--NumBuffers;
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ID.Buffers[NumBuffers] = ProcResourceMasks[I];
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}
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}
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}
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LLVM_DEBUG({
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for (const std::pair<uint64_t, ResourceUsage> &R : ID.Resources)
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dbgs() << "\t\tMask=" << R.first << ", cy=" << R.second.size() << '\n';
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for (const uint64_t R : ID.Buffers)
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dbgs() << "\t\tBuffer Mask=" << R << '\n';
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});
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}
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static void computeMaxLatency(InstrDesc &ID, const MCInstrDesc &MCDesc,
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const MCSchedClassDesc &SCDesc,
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const MCSubtargetInfo &STI) {
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if (MCDesc.isCall()) {
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// We cannot estimate how long this call will take.
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// Artificially set an arbitrarily high latency (100cy).
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ID.MaxLatency = 100U;
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return;
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}
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int Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
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// If latency is unknown, then conservatively assume a MaxLatency of 100cy.
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ID.MaxLatency = Latency < 0 ? 100U : static_cast<unsigned>(Latency);
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}
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static Error verifyOperands(const MCInstrDesc &MCDesc, const MCInst &MCI) {
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// Count register definitions, and skip non register operands in the process.
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unsigned I, E;
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unsigned NumExplicitDefs = MCDesc.getNumDefs();
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for (I = 0, E = MCI.getNumOperands(); NumExplicitDefs && I < E; ++I) {
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const MCOperand &Op = MCI.getOperand(I);
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if (Op.isReg())
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--NumExplicitDefs;
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}
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if (NumExplicitDefs) {
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return make_error<InstructionError<MCInst>>(
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"Expected more register operand definitions.", MCI);
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}
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if (MCDesc.hasOptionalDef()) {
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// Always assume that the optional definition is the last operand.
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const MCOperand &Op = MCI.getOperand(MCDesc.getNumOperands() - 1);
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if (I == MCI.getNumOperands() || !Op.isReg()) {
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std::string Message =
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"expected a register operand for an optional definition. Instruction "
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"has not been correctly analyzed.";
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return make_error<InstructionError<MCInst>>(Message, MCI);
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}
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}
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return ErrorSuccess();
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}
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void InstrBuilder::populateWrites(InstrDesc &ID, const MCInst &MCI,
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unsigned SchedClassID) {
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const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
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const MCSchedModel &SM = STI.getSchedModel();
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const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
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// Assumptions made by this algorithm:
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// 1. The number of explicit and implicit register definitions in a MCInst
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// matches the number of explicit and implicit definitions according to
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// the opcode descriptor (MCInstrDesc).
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// 2. Uses start at index #(MCDesc.getNumDefs()).
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// 3. There can only be a single optional register definition, an it is
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// always the last operand of the sequence (excluding extra operands
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// contributed by variadic opcodes).
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//
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// These assumptions work quite well for most out-of-order in-tree targets
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// like x86. This is mainly because the vast majority of instructions is
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// expanded to MCInst using a straightforward lowering logic that preserves
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// the ordering of the operands.
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//
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// About assumption 1.
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// The algorithm allows non-register operands between register operand
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// definitions. This helps to handle some special ARM instructions with
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// implicit operand increment (-mtriple=armv7):
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//
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// vld1.32 {d18, d19}, [r1]! @ <MCInst #1463 VLD1q32wb_fixed
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// @ <MCOperand Reg:59>
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// @ <MCOperand Imm:0> (!!)
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// @ <MCOperand Reg:67>
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// @ <MCOperand Imm:0>
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// @ <MCOperand Imm:14>
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// @ <MCOperand Reg:0>>
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//
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// MCDesc reports:
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// 6 explicit operands.
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// 1 optional definition
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// 2 explicit definitions (!!)
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//
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// The presence of an 'Imm' operand between the two register definitions
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// breaks the assumption that "register definitions are always at the
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// beginning of the operand sequence".
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//
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// To workaround this issue, this algorithm ignores (i.e. skips) any
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// non-register operands between register definitions. The optional
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// definition is still at index #(NumOperands-1).
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//
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// According to assumption 2. register reads start at #(NumExplicitDefs-1).
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// That means, register R1 from the example is both read and written.
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unsigned NumExplicitDefs = MCDesc.getNumDefs();
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unsigned NumImplicitDefs = MCDesc.getNumImplicitDefs();
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unsigned NumWriteLatencyEntries = SCDesc.NumWriteLatencyEntries;
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unsigned TotalDefs = NumExplicitDefs + NumImplicitDefs;
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if (MCDesc.hasOptionalDef())
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TotalDefs++;
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unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();
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ID.Writes.resize(TotalDefs + NumVariadicOps);
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// Iterate over the operands list, and skip non-register operands.
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// The first NumExplictDefs register operands are expected to be register
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// definitions.
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unsigned CurrentDef = 0;
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unsigned i = 0;
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for (; i < MCI.getNumOperands() && CurrentDef < NumExplicitDefs; ++i) {
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const MCOperand &Op = MCI.getOperand(i);
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if (!Op.isReg())
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continue;
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WriteDescriptor &Write = ID.Writes[CurrentDef];
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Write.OpIndex = i;
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if (CurrentDef < NumWriteLatencyEntries) {
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const MCWriteLatencyEntry &WLE =
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*STI.getWriteLatencyEntry(&SCDesc, CurrentDef);
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// Conservatively default to MaxLatency.
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Write.Latency =
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WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles);
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Write.SClassOrWriteResourceID = WLE.WriteResourceID;
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} else {
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// Assign a default latency for this write.
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Write.Latency = ID.MaxLatency;
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Write.SClassOrWriteResourceID = 0;
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}
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Write.IsOptionalDef = false;
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LLVM_DEBUG({
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dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
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<< ", Latency=" << Write.Latency
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<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
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});
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CurrentDef++;
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}
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assert(CurrentDef == NumExplicitDefs &&
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"Expected more register operand definitions.");
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for (CurrentDef = 0; CurrentDef < NumImplicitDefs; ++CurrentDef) {
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unsigned Index = NumExplicitDefs + CurrentDef;
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WriteDescriptor &Write = ID.Writes[Index];
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Write.OpIndex = ~CurrentDef;
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Write.RegisterID = MCDesc.getImplicitDefs()[CurrentDef];
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if (Index < NumWriteLatencyEntries) {
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const MCWriteLatencyEntry &WLE =
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*STI.getWriteLatencyEntry(&SCDesc, Index);
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// Conservatively default to MaxLatency.
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Write.Latency =
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WLE.Cycles < 0 ? ID.MaxLatency : static_cast<unsigned>(WLE.Cycles);
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Write.SClassOrWriteResourceID = WLE.WriteResourceID;
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} else {
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// Assign a default latency for this write.
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Write.Latency = ID.MaxLatency;
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Write.SClassOrWriteResourceID = 0;
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}
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Write.IsOptionalDef = false;
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assert(Write.RegisterID != 0 && "Expected a valid phys register!");
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LLVM_DEBUG({
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dbgs() << "\t\t[Def][I] OpIdx=" << ~Write.OpIndex
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<< ", PhysReg=" << MRI.getName(Write.RegisterID)
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<< ", Latency=" << Write.Latency
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<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
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});
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}
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if (MCDesc.hasOptionalDef()) {
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WriteDescriptor &Write = ID.Writes[NumExplicitDefs + NumImplicitDefs];
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Write.OpIndex = MCDesc.getNumOperands() - 1;
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// Assign a default latency for this write.
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Write.Latency = ID.MaxLatency;
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Write.SClassOrWriteResourceID = 0;
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Write.IsOptionalDef = true;
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LLVM_DEBUG({
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dbgs() << "\t\t[Def][O] OpIdx=" << Write.OpIndex
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<< ", Latency=" << Write.Latency
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<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
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});
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}
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if (!NumVariadicOps)
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return;
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// FIXME: if an instruction opcode is flagged 'mayStore', and it has no
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// "unmodeledSideEffects', then this logic optimistically assumes that any
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// extra register operands in the variadic sequence is not a register
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// definition.
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//
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// Otherwise, we conservatively assume that any register operand from the
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// variadic sequence is both a register read and a register write.
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bool AssumeUsesOnly = MCDesc.mayStore() && !MCDesc.mayLoad() &&
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!MCDesc.hasUnmodeledSideEffects();
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CurrentDef = NumExplicitDefs + NumImplicitDefs + MCDesc.hasOptionalDef();
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for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
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I < NumVariadicOps && !AssumeUsesOnly; ++I, ++OpIndex) {
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const MCOperand &Op = MCI.getOperand(OpIndex);
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if (!Op.isReg())
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continue;
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WriteDescriptor &Write = ID.Writes[CurrentDef];
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Write.OpIndex = OpIndex;
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// Assign a default latency for this write.
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Write.Latency = ID.MaxLatency;
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Write.SClassOrWriteResourceID = 0;
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Write.IsOptionalDef = false;
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++CurrentDef;
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LLVM_DEBUG({
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dbgs() << "\t\t[Def][V] OpIdx=" << Write.OpIndex
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<< ", Latency=" << Write.Latency
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<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
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});
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}
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ID.Writes.resize(CurrentDef);
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}
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void InstrBuilder::populateReads(InstrDesc &ID, const MCInst &MCI,
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unsigned SchedClassID) {
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const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
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unsigned NumExplicitUses = MCDesc.getNumOperands() - MCDesc.getNumDefs();
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unsigned NumImplicitUses = MCDesc.getNumImplicitUses();
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// Remove the optional definition.
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if (MCDesc.hasOptionalDef())
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--NumExplicitUses;
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unsigned NumVariadicOps = MCI.getNumOperands() - MCDesc.getNumOperands();
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unsigned TotalUses = NumExplicitUses + NumImplicitUses + NumVariadicOps;
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ID.Reads.resize(TotalUses);
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unsigned CurrentUse = 0;
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for (unsigned I = 0, OpIndex = MCDesc.getNumDefs(); I < NumExplicitUses;
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++I, ++OpIndex) {
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const MCOperand &Op = MCI.getOperand(OpIndex);
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if (!Op.isReg())
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continue;
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ReadDescriptor &Read = ID.Reads[CurrentUse];
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Read.OpIndex = OpIndex;
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Read.UseIndex = I;
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Read.SchedClassID = SchedClassID;
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++CurrentUse;
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LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex
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<< ", UseIndex=" << Read.UseIndex << '\n');
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}
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// For the purpose of ReadAdvance, implicit uses come directly after explicit
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// uses. The "UseIndex" must be updated according to that implicit layout.
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for (unsigned I = 0; I < NumImplicitUses; ++I) {
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ReadDescriptor &Read = ID.Reads[CurrentUse + I];
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Read.OpIndex = ~I;
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Read.UseIndex = NumExplicitUses + I;
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Read.RegisterID = MCDesc.getImplicitUses()[I];
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Read.SchedClassID = SchedClassID;
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LLVM_DEBUG(dbgs() << "\t\t[Use][I] OpIdx=" << ~Read.OpIndex
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<< ", UseIndex=" << Read.UseIndex << ", RegisterID="
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<< MRI.getName(Read.RegisterID) << '\n');
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}
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CurrentUse += NumImplicitUses;
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// FIXME: If an instruction opcode is marked as 'mayLoad', and it has no
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// "unmodeledSideEffects", then this logic optimistically assumes that any
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// extra register operands in the variadic sequence are not register
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// definition.
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bool AssumeDefsOnly = !MCDesc.mayStore() && MCDesc.mayLoad() &&
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!MCDesc.hasUnmodeledSideEffects();
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for (unsigned I = 0, OpIndex = MCDesc.getNumOperands();
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I < NumVariadicOps && !AssumeDefsOnly; ++I, ++OpIndex) {
|
|
const MCOperand &Op = MCI.getOperand(OpIndex);
|
|
if (!Op.isReg())
|
|
continue;
|
|
|
|
ReadDescriptor &Read = ID.Reads[CurrentUse];
|
|
Read.OpIndex = OpIndex;
|
|
Read.UseIndex = NumExplicitUses + NumImplicitUses + I;
|
|
Read.SchedClassID = SchedClassID;
|
|
++CurrentUse;
|
|
LLVM_DEBUG(dbgs() << "\t\t[Use][V] OpIdx=" << Read.OpIndex
|
|
<< ", UseIndex=" << Read.UseIndex << '\n');
|
|
}
|
|
|
|
ID.Reads.resize(CurrentUse);
|
|
}
|
|
|
|
Error InstrBuilder::verifyInstrDesc(const InstrDesc &ID,
|
|
const MCInst &MCI) const {
|
|
if (ID.NumMicroOps != 0)
|
|
return ErrorSuccess();
|
|
|
|
bool UsesMemory = ID.MayLoad || ID.MayStore;
|
|
bool UsesBuffers = !ID.Buffers.empty();
|
|
bool UsesResources = !ID.Resources.empty();
|
|
if (!UsesMemory && !UsesBuffers && !UsesResources)
|
|
return ErrorSuccess();
|
|
|
|
StringRef Message;
|
|
if (UsesMemory) {
|
|
Message = "found an inconsistent instruction that decodes "
|
|
"into zero opcodes and that consumes load/store "
|
|
"unit resources.";
|
|
} else {
|
|
Message = "found an inconsistent instruction that decodes "
|
|
"to zero opcodes and that consumes scheduler "
|
|
"resources.";
|
|
}
|
|
|
|
return make_error<InstructionError<MCInst>>(Message, MCI);
|
|
}
|
|
|
|
Expected<const InstrDesc &>
|
|
InstrBuilder::createInstrDescImpl(const MCInst &MCI) {
|
|
assert(STI.getSchedModel().hasInstrSchedModel() &&
|
|
"Itineraries are not yet supported!");
|
|
|
|
// Obtain the instruction descriptor from the opcode.
|
|
unsigned short Opcode = MCI.getOpcode();
|
|
const MCInstrDesc &MCDesc = MCII.get(Opcode);
|
|
const MCSchedModel &SM = STI.getSchedModel();
|
|
|
|
// Then obtain the scheduling class information from the instruction.
|
|
unsigned SchedClassID = MCDesc.getSchedClass();
|
|
bool IsVariant = SM.getSchedClassDesc(SchedClassID)->isVariant();
|
|
|
|
// Try to solve variant scheduling classes.
|
|
if (IsVariant) {
|
|
unsigned CPUID = SM.getProcessorID();
|
|
while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
|
|
SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &MCI, CPUID);
|
|
|
|
if (!SchedClassID) {
|
|
return make_error<InstructionError<MCInst>>(
|
|
"unable to resolve scheduling class for write variant.", MCI);
|
|
}
|
|
}
|
|
|
|
// Check if this instruction is supported. Otherwise, report an error.
|
|
const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
|
|
if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
|
|
return make_error<InstructionError<MCInst>>(
|
|
"found an unsupported instruction in the input assembly sequence.",
|
|
MCI);
|
|
}
|
|
|
|
// Create a new empty descriptor.
|
|
std::unique_ptr<InstrDesc> ID = llvm::make_unique<InstrDesc>();
|
|
ID->NumMicroOps = SCDesc.NumMicroOps;
|
|
|
|
if (MCDesc.isCall() && FirstCallInst) {
|
|
// We don't correctly model calls.
|
|
WithColor::warning() << "found a call in the input assembly sequence.\n";
|
|
WithColor::note() << "call instructions are not correctly modeled. "
|
|
<< "Assume a latency of 100cy.\n";
|
|
FirstCallInst = false;
|
|
}
|
|
|
|
if (MCDesc.isReturn() && FirstReturnInst) {
|
|
WithColor::warning() << "found a return instruction in the input"
|
|
<< " assembly sequence.\n";
|
|
WithColor::note() << "program counter updates are ignored.\n";
|
|
FirstReturnInst = false;
|
|
}
|
|
|
|
ID->MayLoad = MCDesc.mayLoad();
|
|
ID->MayStore = MCDesc.mayStore();
|
|
ID->HasSideEffects = MCDesc.hasUnmodeledSideEffects();
|
|
ID->BeginGroup = SCDesc.BeginGroup;
|
|
ID->EndGroup = SCDesc.EndGroup;
|
|
|
|
initializeUsedResources(*ID, SCDesc, STI, ProcResourceMasks);
|
|
computeMaxLatency(*ID, MCDesc, SCDesc, STI);
|
|
|
|
if (Error Err = verifyOperands(MCDesc, MCI))
|
|
return std::move(Err);
|
|
|
|
populateWrites(*ID, MCI, SchedClassID);
|
|
populateReads(*ID, MCI, SchedClassID);
|
|
|
|
LLVM_DEBUG(dbgs() << "\t\tMaxLatency=" << ID->MaxLatency << '\n');
|
|
LLVM_DEBUG(dbgs() << "\t\tNumMicroOps=" << ID->NumMicroOps << '\n');
|
|
|
|
// Sanity check on the instruction descriptor.
|
|
if (Error Err = verifyInstrDesc(*ID, MCI))
|
|
return std::move(Err);
|
|
|
|
// Now add the new descriptor.
|
|
SchedClassID = MCDesc.getSchedClass();
|
|
bool IsVariadic = MCDesc.isVariadic();
|
|
if (!IsVariadic && !IsVariant) {
|
|
Descriptors[MCI.getOpcode()] = std::move(ID);
|
|
return *Descriptors[MCI.getOpcode()];
|
|
}
|
|
|
|
VariantDescriptors[&MCI] = std::move(ID);
|
|
return *VariantDescriptors[&MCI];
|
|
}
|
|
|
|
Expected<const InstrDesc &>
|
|
InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
|
|
if (Descriptors.find_as(MCI.getOpcode()) != Descriptors.end())
|
|
return *Descriptors[MCI.getOpcode()];
|
|
|
|
if (VariantDescriptors.find(&MCI) != VariantDescriptors.end())
|
|
return *VariantDescriptors[&MCI];
|
|
|
|
return createInstrDescImpl(MCI);
|
|
}
|
|
|
|
Expected<std::unique_ptr<Instruction>>
|
|
InstrBuilder::createInstruction(const MCInst &MCI) {
|
|
Expected<const InstrDesc &> DescOrErr = getOrCreateInstrDesc(MCI);
|
|
if (!DescOrErr)
|
|
return DescOrErr.takeError();
|
|
const InstrDesc &D = *DescOrErr;
|
|
std::unique_ptr<Instruction> NewIS = llvm::make_unique<Instruction>(D);
|
|
|
|
// Check if this is a dependency breaking instruction.
|
|
APInt Mask;
|
|
|
|
bool IsZeroIdiom = false;
|
|
bool IsDepBreaking = false;
|
|
if (MCIA) {
|
|
unsigned ProcID = STI.getSchedModel().getProcessorID();
|
|
IsZeroIdiom = MCIA->isZeroIdiom(MCI, Mask, ProcID);
|
|
IsDepBreaking =
|
|
IsZeroIdiom || MCIA->isDependencyBreaking(MCI, Mask, ProcID);
|
|
if (MCIA->isOptimizableRegisterMove(MCI, ProcID))
|
|
NewIS->setOptimizableMove();
|
|
}
|
|
|
|
// Initialize Reads first.
|
|
for (const ReadDescriptor &RD : D.Reads) {
|
|
int RegID = -1;
|
|
if (!RD.isImplicitRead()) {
|
|
// explicit read.
|
|
const MCOperand &Op = MCI.getOperand(RD.OpIndex);
|
|
// Skip non-register operands.
|
|
if (!Op.isReg())
|
|
continue;
|
|
RegID = Op.getReg();
|
|
} else {
|
|
// Implicit read.
|
|
RegID = RD.RegisterID;
|
|
}
|
|
|
|
// Skip invalid register operands.
|
|
if (!RegID)
|
|
continue;
|
|
|
|
// Okay, this is a register operand. Create a ReadState for it.
|
|
assert(RegID > 0 && "Invalid register ID found!");
|
|
NewIS->getUses().emplace_back(RD, RegID);
|
|
ReadState &RS = NewIS->getUses().back();
|
|
|
|
if (IsDepBreaking) {
|
|
// A mask of all zeroes means: explicit input operands are not
|
|
// independent.
|
|
if (Mask.isNullValue()) {
|
|
if (!RD.isImplicitRead())
|
|
RS.setIndependentFromDef();
|
|
} else {
|
|
// Check if this register operand is independent according to `Mask`.
|
|
// Note that Mask may not have enough bits to describe all explicit and
|
|
// implicit input operands. If this register operand doesn't have a
|
|
// corresponding bit in Mask, then conservatively assume that it is
|
|
// dependent.
|
|
if (Mask.getBitWidth() > RD.UseIndex) {
|
|
// Okay. This map describe register use `RD.UseIndex`.
|
|
if (Mask[RD.UseIndex])
|
|
RS.setIndependentFromDef();
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
// Early exit if there are no writes.
|
|
if (D.Writes.empty())
|
|
return std::move(NewIS);
|
|
|
|
// Track register writes that implicitly clear the upper portion of the
|
|
// underlying super-registers using an APInt.
|
|
APInt WriteMask(D.Writes.size(), 0);
|
|
|
|
// Now query the MCInstrAnalysis object to obtain information about which
|
|
// register writes implicitly clear the upper portion of a super-register.
|
|
if (MCIA)
|
|
MCIA->clearsSuperRegisters(MRI, MCI, WriteMask);
|
|
|
|
// Initialize writes.
|
|
unsigned WriteIndex = 0;
|
|
for (const WriteDescriptor &WD : D.Writes) {
|
|
unsigned RegID = WD.isImplicitWrite() ? WD.RegisterID
|
|
: MCI.getOperand(WD.OpIndex).getReg();
|
|
// Check if this is a optional definition that references NoReg.
|
|
if (WD.IsOptionalDef && !RegID) {
|
|
++WriteIndex;
|
|
continue;
|
|
}
|
|
|
|
assert(RegID && "Expected a valid register ID!");
|
|
NewIS->getDefs().emplace_back(WD, RegID,
|
|
/* ClearsSuperRegs */ WriteMask[WriteIndex],
|
|
/* WritesZero */ IsZeroIdiom);
|
|
++WriteIndex;
|
|
}
|
|
|
|
return std::move(NewIS);
|
|
}
|
|
} // namespace mca
|
|
} // namespace llvm
|