llvm-project/llvm/test/CodeGen
Craig Topper a362dee774 [X86] Remove AND32ri8 from pattern for v1i1 load.
I don't think anything would actually expect the other bits to be zero.

llvm-svn: 321596
2017-12-31 07:38:33 +00:00
..
AArch64 [AArch64] Change order of candidate FMLS patterns 2017-12-27 15:25:01 +00:00
AMDGPU 2nd attempt at "fixing" amdgpu tests after r321575​ 2017-12-31 03:34:36 +00:00
ARC
ARM [ARM GlobalISel] Support G_INTTOPTR and G_PTRTOINT for s32 2017-12-22 13:05:51 +00:00
AVR [AVR] Fix two CodeGen tests 2017-12-09 07:51:43 +00:00
BPF bpf: add support for objdump -print-imm-hex 2017-12-20 19:39:58 +00:00
Generic [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Hexagon [Hexagon] Allow construction of HVX vector predicates 2017-12-20 20:49:43 +00:00
Inputs
Lanai [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
MIR [YAML] Add support for non-printable characters 2017-12-18 17:38:03 +00:00
MSP430 [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Mips [mips] Replace assert by an error message 2017-12-29 19:18:24 +00:00
NVPTX [Memcpy Loop Lowering] Remove the fixed int8 lowering. 2017-12-18 15:31:14 +00:00
Nios2 [Nios2] final infrastructure to provide compilation of a return from a function 2017-12-07 12:35:02 +00:00
PowerPC [PowerPC] fix a bug in TCO eligibility check 2017-12-30 08:09:04 +00:00
RISCV [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
SPARC Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion 2017-12-11 22:25:04 +00:00
SystemZ [MachineOperand][MIR] Add isRenamable to MachineOperand. 2017-12-12 17:53:59 +00:00
Thumb [ARM] Add tests for D34515 2017-12-15 09:24:46 +00:00
Thumb2 [ARM] Register the Thumb2SizeReducePass. NFC 2017-12-19 12:19:08 +00:00
WebAssembly [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors 2017-12-15 00:17:10 +00:00
WinEH Make x86 __ehhandler comdat if parent function is 2017-10-20 17:04:43 +00:00
X86 [X86] Remove AND32ri8 from pattern for v1i1 load. 2017-12-31 07:38:33 +00:00
XCore