llvm-project/llvm/test/MC/Disassembler/X86
Maksim Panchenko 89e4abe7b7 [X86][Disassembler] Fix LOCK prefix disassembler support
Summary:
If LOCK prefix is not the first prefix in an instruction, LLVM
disassembler silently drops the prefix.

The fix is to select a proper instruction with a builtin LOCK prefix if
one exists.

Reviewers: craig.topper

Reviewed By: craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D49001

llvm-svn: 336400
2018-07-05 23:32:42 +00:00
..
amd3dnow.txt [X86][3DNow!] Add PFRCP reg-reg disassembler test case (PR21168) 2018-02-17 14:58:16 +00:00
avx-512.txt [X86] Properly disassemble gather/scatter instructions where xmm4/ymm4/zmm4 are used as the index. 2018-06-06 19:15:15 +00:00
fp-stack.txt [X86] Run dos2unix on two disassembler tests. 2017-10-02 21:46:58 +00:00
gather-novsib.txt [X86] Don't allow gather/scatter to disassembler if memory operand does not use a SIB byte. 2017-10-22 04:32:30 +00:00
hex-immediates.txt
intel-syntax-32.txt [X86] Remove 'opaque ptr' from the intel syntax parser and printer. 2018-05-01 04:42:00 +00:00
intel-syntax.txt [X86] Remove 'opaque ptr' from the intel syntax parser and printer. 2018-05-01 04:42:00 +00:00
invalid-EVEX-R2.txt [X86][Disassembler] Make it an error to set EVEX.R' to 0 when modrm.reg encodes a GPR. 2018-06-01 06:11:29 +00:00
invalid-VEX-vvvv-32.txt [X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode. 2018-06-01 01:23:52 +00:00
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
missing-sib.txt
moffs.txt
padlock.txt
prefixes-i386.txt Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
prefixes-x86_64.txt Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
prefixes.txt [X86][Disassembler] Fix LOCK prefix disassembler support 2018-07-05 23:32:42 +00:00
simple-tests.txt [X86] Add 'l' and 'q' suffixes to the tbm instruction mnemonics. 2018-01-12 06:21:36 +00:00
truncated-input.txt
x86-16.txt [X86] movdiri and movdir64b instructions 2018-05-01 10:01:16 +00:00
x86-32.txt [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. 2018-06-27 19:03:36 +00:00
x86-64-err.txt [X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. 2017-10-22 06:18:26 +00:00
x86-64.txt [X86] Teach the disassembler to use %eiz/%riz instead of NoRegister when the SIB byte is present, but doesn't encode an index register and there was another shorter encoding that would achieve the same result. 2018-06-27 19:03:36 +00:00