forked from OSchip/llvm-project
210 lines
6.7 KiB
ReStructuredText
210 lines
6.7 KiB
ReStructuredText
llvm-mca - LLVM Machine Code Analyzer
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=====================================
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SYNOPSIS
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--------
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:program:`llvm-mca` [*options*] [input]
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DESCRIPTION
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-----------
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:program:`llvm-mca` is a performance analysis tool that uses information
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available in LLVM (e.g. scheduling models) to statically measure the performance
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of machine code in a specific CPU.
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Performance is measured in terms of throughput as well as processor resource
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consumption. The tool currently works for processors with an out-of-order
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backend, for which there is a scheduling model available in LLVM.
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The main goal of this tool is not just to predict the performance of the code
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when run on the target, but also help with diagnosing potential performance
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issues.
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Given an assembly code sequence, llvm-mca estimates the IPC (Instructions Per
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Cycle), as well as hardware resource pressure. The analysis and reporting style
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were inspired by the IACA tool from Intel.
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:program:`llvm-mca` allows the usage of special code comments to mark regions of
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the assembly code to be analyzed. A comment starting with substring
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``LLVM-MCA-BEGIN`` marks the beginning of a code region. A comment starting with
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substring ``LLVM-MCA-END`` marks the end of a code region. For example:
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.. code-block:: none
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# LLVM-MCA-BEGIN My Code Region
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...
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# LLVM-MCA-END
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Multiple regions can be specified provided that they do not overlap. A code
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region can have an optional description. If no user-defined region is specified,
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then :program:`llvm-mca` assumes a default region which contains every
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instruction in the input file. Every region is analyzed in isolation, and the
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final performance report is the union of all the reports generated for every
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code region.
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Inline assembly directives may be used from source code to annotate the
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assembly text:
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.. code-block:: c++
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int foo(int a, int b) {
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__asm volatile("# LLVM-MCA-BEGIN foo");
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a += 42;
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__asm volatile("# LLVM-MCA-END");
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a *= b;
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return a;
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}
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So for example, you can compile code with clang, output assembly, and pipe it
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directly into llvm-mca for analysis:
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.. code-block:: bash
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$ clang foo.c -O2 -target x86_64-unknown-unknown -S -o - | llvm-mca -mcpu=btver2
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Or for Intel syntax:
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.. code-block:: bash
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$ clang foo.c -O2 -target x86_64-unknown-unknown -mllvm -x86-asm-syntax=intel -S -o - | llvm-mca -mcpu=btver2
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OPTIONS
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-------
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If ``input`` is "``-``" or omitted, :program:`llvm-mca` reads from standard
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input. Otherwise, it will read from the specified filename.
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If the :option:`-o` option is omitted, then :program:`llvm-mca` will send its output
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to standard output if the input is from standard input. If the :option:`-o`
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option specifies "``-``", then the output will also be sent to standard output.
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.. option:: -help
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Print a summary of command line options.
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.. option:: -mtriple=<target triple>
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Specify a target triple string.
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.. option:: -march=<arch>
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Specify the architecture for which to analyze the code. It defaults to the
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host default target.
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.. option:: -mcpu=<cpuname>
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Specify the processor for which to analyze the code. By default, the cpu name
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is autodetected from the host.
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.. option:: -output-asm-variant=<variant id>
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Specify the output assembly variant for the report generated by the tool.
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On x86, possible values are [0, 1]. A value of 0 (vic. 1) for this flag enables
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the AT&T (vic. Intel) assembly format for the code printed out by the tool in
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the analysis report.
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.. option:: -dispatch=<width>
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Specify a different dispatch width for the processor. The dispatch width
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defaults to field 'IssueWidth' in the processor scheduling model. If width is
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zero, then the default dispatch width is used.
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.. option:: -register-file-size=<size>
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Specify the size of the register file. When specified, this flag limits how
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many temporary registers are available for register renaming purposes. A value
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of zero for this flag means "unlimited number of temporary registers".
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.. option:: -iterations=<number of iterations>
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Specify the number of iterations to run. If this flag is set to 0, then the
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tool sets the number of iterations to a default value (i.e. 100).
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.. option:: -noalias=<bool>
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If set, the tool assumes that loads and stores don't alias. This is the
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default behavior.
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.. option:: -lqueue=<load queue size>
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Specify the size of the load queue in the load/store unit emulated by the tool.
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By default, the tool assumes an unbound number of entries in the load queue.
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A value of zero for this flag is ignored, and the default load queue size is
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used instead.
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.. option:: -squeue=<store queue size>
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Specify the size of the store queue in the load/store unit emulated by the
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tool. By default, the tool assumes an unbound number of entries in the store
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queue. A value of zero for this flag is ignored, and the default store queue
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size is used instead.
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.. option:: -timeline
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Enable the timeline view.
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.. option:: -timeline-max-iterations=<iterations>
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Limit the number of iterations to print in the timeline view. By default, the
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timeline view prints information for up to 10 iterations.
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.. option:: -timeline-max-cycles=<cycles>
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Limit the number of cycles in the timeline view. By default, the number of
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cycles is set to 80.
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.. option:: -resource-pressure
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Enable the resource pressure view. This is enabled by default.
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.. option:: -register-file-stats
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Enable register file usage statistics.
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.. option:: -dispatch-stats
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Enable extra dispatch statistics. This view collects and analyzes instruction
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dispatch events, as well as static/dynamic dispatch stall events. This view
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is disabled by default.
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.. option:: -scheduler-stats
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Enable extra scheduler statistics. This view collects and analyzes instruction
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issue events. This view is disabled by default.
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.. option:: -retire-stats
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Enable extra retire control unit statistics. This view is disabled by default.
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.. option:: -instruction-info
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Enable the instruction info view. This is enabled by default.
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.. option:: -all-stats
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Print all hardware statistics. This enables extra statistics related to the
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dispatch logic, the hardware schedulers, the register file(s), and the retire
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control unit. This option is disabled by default.
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.. option:: -all-views
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Enable all the view.
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.. option:: -instruction-tables
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Prints resource pressure information based on the static information
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available from the processor model. This differs from the resource pressure
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view because it doesn't require that the code is simulated. It instead prints
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the theoretical uniform distribution of resource pressure for every
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instruction in sequence.
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EXIT STATUS
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-----------
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:program:`llvm-mca` returns 0 on success. Otherwise, an error message is printed
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to standard error, and the tool returns 1.
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