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AsmParser
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[NFC] fix trivial typos in comments and error message
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2018-04-09 04:37:53 +00:00 |
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Disassembler
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[RISCV] Implement c.lui immediate operand constraint
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2018-02-22 15:02:28 +00:00 |
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InstPrinter
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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MCTargetDesc
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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TargetInfo
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Fix RISCV build after r318352
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2017-11-16 18:39:31 +00:00 |
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CMakeLists.txt
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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LLVMBuild.txt
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCV.h
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[RISCV] Codegen support for memory operations on global addresses
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2017-11-08 13:24:21 +00:00 |
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RISCV.td
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[MachineOperand][Target] MachineOperand::isRenamable semantics changes
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2018-02-23 18:25:08 +00:00 |
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RISCVAsmPrinter.cpp
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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RISCVCallingConv.td
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[RISCV] Add custom CC_RISCV calling convention and improved call support
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2017-12-11 12:49:02 +00:00 |
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RISCVFrameLowering.cpp
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[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
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2018-03-20 01:39:17 +00:00 |
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RISCVFrameLowering.h
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[RISCV] Preserve stack space for outgoing arguments when the function contain variable size objects
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2018-03-20 01:39:17 +00:00 |
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RISCVISelDAGToDAG.cpp
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[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
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2018-04-12 05:34:25 +00:00 |
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RISCVISelLowering.cpp
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[RISCV] Codegen support for RV32D floating point conversion operations
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2018-04-12 05:47:15 +00:00 |
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RISCVISelLowering.h
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[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
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2018-04-12 05:34:25 +00:00 |
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RISCVInstrFormats.td
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[RISCV] MC layer support for load/store instructions of the C (compressed) extension
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2017-12-07 12:50:32 +00:00 |
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RISCVInstrFormatsC.td
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[RISCV] MC layer support for the remaining RVC instructions
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2017-12-13 09:32:55 +00:00 |
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RISCVInstrInfo.cpp
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[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
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2018-04-12 05:34:25 +00:00 |
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RISCVInstrInfo.h
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[RISCV] Implement support for the BranchRelaxation pass
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2018-01-10 21:05:07 +00:00 |
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RISCVInstrInfo.td
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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RISCVInstrInfoA.td
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[RISCV] MC layer support for the standard RV64A instruction set extension
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2017-12-07 10:59:12 +00:00 |
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RISCVInstrInfoC.td
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[RISCV] Tablegen-driven Instruction Compression.
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2018-04-06 21:07:05 +00:00 |
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RISCVInstrInfoD.td
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[RISCV] Codegen support for RV32D floating point conversion operations
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2018-04-12 05:47:15 +00:00 |
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RISCVInstrInfoF.td
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[RISCV] Codegen support for RV32F floating point comparison operations
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2018-03-21 15:11:02 +00:00 |
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RISCVInstrInfoM.td
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[RISCV] Codegen support for the standard RV32M instruction set extension
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2018-01-18 12:36:38 +00:00 |
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RISCVMCInstLower.cpp
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[RISCV] Add codegen for RV32F floating point load/store
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2018-03-20 13:26:12 +00:00 |
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RISCVMachineFunctionInfo.h
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[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv
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2018-04-12 05:34:25 +00:00 |
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RISCVRegisterInfo.cpp
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[RISCV] Implement frame pointer elimination
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2018-01-18 11:34:02 +00:00 |
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RISCVRegisterInfo.h
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[RISCV] Implement support for the BranchRelaxation pass
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2018-01-10 21:05:07 +00:00 |
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RISCVRegisterInfo.td
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[RISCV] MC layer support for the remaining RVC instructions
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2017-12-13 09:32:55 +00:00 |
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RISCVSubtarget.cpp
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVSubtarget.h
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[RISCV] MC layer support for load/store instructions of the C (compressed) extension
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2017-12-07 12:50:32 +00:00 |
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RISCVTargetMachine.cpp
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |
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RISCVTargetMachine.h
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[RISCV] Initial codegen support for ALU operations
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2017-10-19 21:37:38 +00:00 |
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RISCVTargetObjectFile.cpp
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |
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RISCVTargetObjectFile.h
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[RISCV] Use init_array instead of ctors for RISCV target, by default
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2018-03-24 18:37:19 +00:00 |
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