llvm-project/llvm/test/CodeGen
Andy Wingo 9ac5620cb8 [WebAssembly] Rename WasmLimits::Initial to ::Minimum. NFC.
This patch renames the "Initial" member of WasmLimits to the name used
in the spec, "Minimum".

In the core WebAssembly specification, the Limits data type has one
required "min" member and one optional "max" member, indicating the
minimum required size of the corresponding table or memory, and the
maximum size, if any.

Although the WebAssembly spec does instantiate locally-defined tables
and memories with the initial size being equal to the minimum size, it
can't impose such a requirement for imports.  It doesn't make sense to
require an initial size for a memory import, for example.  The compiler
can only sensibly express the minimum and maximum sizes.

See
https://github.com/WebAssembly/js-types/blob/master/proposals/js-types/Overview.md#naming-of-size-limits
for a related discussion that agrees that the right name of "initial" is
"minimum" when querying the type of a table or memory from JavaScript.
(Of course it still makes sense for JS to speak in terms of an initial
size when it explicitly instantiates memories and tables.)

Differential Revision: https://reviews.llvm.org/D99186
2021-03-24 09:10:11 +01:00
..
AArch64 [AArch64][GlobalISel] Add test for G_FSHR legalization. 2021-03-23 16:11:45 -07:00
AMDGPU GlobalISel: Lower funnel shifts 2021-03-23 09:11:17 -04:00
ARC
ARM [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
AVR [AVR] Fix lifeness issues in the AVR backend 2021-03-04 14:04:39 +01:00
BPF [BPF] Add support for floats and doubles 2021-03-05 15:10:11 +01:00
Generic Temporarily revert "[lli] Make -jit-kind=orc the default JIT engine" 2021-03-23 12:01:30 +01:00
Hexagon [Hexagon] Add support for named registers cs0 and cs1 2021-03-18 09:53:22 -05:00
Inputs
Lanai
M68k [DAG] computeKnownBits - add ISD::MULHS/MULHU/SMUL_LOHI/UMUL_LOHI handling 2021-03-19 16:02:31 +00:00
MIR MIR: Fix missing serialization for HasTailCall 2021-03-21 13:14:04 -04:00
MSP430
Mips Test cases for rem-seteq fold with illegal types 2021-03-12 16:28:04 +02:00
NVPTX [NVPTX] CUDA does provide malloc/free since compute capability 2.X 2021-03-15 22:45:56 -05:00
PowerPC [PowerPC] Enable redundant TOC save removal on AIX 2021-03-22 14:29:22 +08:00
RISCV [RISCV] Further optimize BUILD_VECTORs with repeated elements 2021-03-23 14:14:48 +00:00
SPARC [LegalizeTypes] Improve ExpandIntRes_XMULO codegen. 2021-03-01 09:54:32 -08:00
SystemZ [SystemZ] Reimplement the i8/i16 compare-and-swap logic. 2021-03-03 14:04:32 -06:00
Thumb [ARM] Use lrdsb for more thumb1 loads. 2021-03-17 15:29:02 +00:00
Thumb2 [ARM] Handle debug instrs in ARM Low Overhead Loop pass 2021-03-23 11:49:06 +00:00
VE [test] Fix CodeGen/VE/Scalar tests 2021-03-02 15:30:44 -08:00
WebAssembly [WebAssembly] Rename WasmLimits::Initial to ::Minimum. NFC. 2021-03-24 09:10:11 +01:00
WinCFGuard
WinEH
X86 [RegAlloc] Fix "ran out of regs" with uses in statepoint 2021-03-24 10:25:34 +07:00
XCore [CodeGen] Report a normal instead of fatal error for label redefinition 2021-03-09 10:54:41 +00:00