llvm-project/llvm/test/CodeGen
Petar Jovanovic f11daad18d [mips] Generate NMADD and NMSUB instructions when fneg node is present
This patch enables generation of NMADD and NMSUB instructions when fneg node
is present. These instructions are currently only generated if fsub node is
present.

Patch by Stanislav Ocovaj.

Differential Revision: https://reviews.llvm.org/D34507

llvm-svn: 311862
2017-08-27 21:07:24 +00:00
..
AArch64 [GISel]: Implement widenScalar for Legalizing G_PHI 2017-08-25 04:57:27 +00:00
AMDGPU IPRA: Don't assume called function is first call operand 2017-08-24 07:55:15 +00:00
ARC [ARC] Add ARC backend. 2017-08-24 15:40:33 +00:00
ARM [ARM] Check for assembler instructions in test. 2017-08-23 11:53:24 +00:00
AVR [AVR] Use the correct register classes for 16-bit atomic operations 2017-08-24 00:14:38 +00:00
BPF bpf: add variants of -mcpu=# and support for additional jmp insns 2017-08-23 04:25:57 +00:00
Generic [TargetPassConfig] Feature generic options to setup start/stop-after/before 2017-07-31 18:24:07 +00:00
Hexagon [Hexagon] Generate correct runtime check when recognizing memmove 2017-08-24 11:59:53 +00:00
Inputs
Lanai
MIR Parse and print DIExpressions inline to ease IR and MIR testing 2017-08-23 20:31:27 +00:00
MSP430 [DAG] Improve Aliasing of operations to static alloca 2017-07-18 20:06:24 +00:00
Mips [mips] Generate NMADD and NMSUB instructions when fneg node is present 2017-08-27 21:07:24 +00:00
NVPTX [NVPTX] Add lowering of i128 params. 2017-07-20 21:16:03 +00:00
Nios2
PowerPC [DAG] convert vector select-of-constants to logic/math 2017-08-24 23:24:43 +00:00
SPARC Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding" round 2 2017-08-18 01:43:11 +00:00
SystemZ [SystemZ, MachineScheduler] Improve post-RA scheduling. 2017-08-17 08:33:44 +00:00
Thumb [ARM, Thumb1] Prevent ARMTargetLowering::isLegalAddressingMode from accepting illegal modes 2017-08-24 10:00:25 +00:00
Thumb2 [ARM] Call setBooleanContents(ZeroOrOneBooleanContent) 2017-08-22 11:02:37 +00:00
WebAssembly [WebAssembly] FastISel : Bail to SelectionDAG for constexpr calls 2017-08-24 19:53:44 +00:00
WinEH
X86 [AVX512] Add more patterns for using masked moves for subvector extracts of the lowest subvector. This time with bitcasts between the vselect and the extract. 2017-08-27 19:03:36 +00:00
XCore Delete Default and JITDefault code models 2017-08-03 02:16:21 +00:00