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llvm-project/llvm/test/CodeGen/RISCV/rvv
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Craig Topper dc00cbb505 [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. 
Limited to splats because we would need to truncate the shift
amount vector otherwise.

I tried to do this with new ISD nodes and a DAG combine to
avoid such a large pattern, but we don't form the splat until
LegalizeDAG and need DAG combine to remove a scalable->fixed->scalable
cast before it becomes visible to the shift node. By the time that
happens we've already visited the truncate node and won't revisit it.

I think I have an idea how to improve i64 on RV32 I'll save for a
follow up.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D102019
 		2021-05-11 09:29:31 -07:00
..
abs-sdnode.ll [RISCV] Optimize fixed vector ABS. Fix crash on scalable vector ABS for SEW=64 with RV32. 2021-03-09 08:51:03 -08:00
access-fixed-objects-by-rvv.ll [RISCV] Fix missing emergency slots for scalable stack offsets 2021-04-20 09:59:41 +01:00
add-vsetvli-gpr.mir [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
add-vsetvli-vlmax.ll [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
addi-scalable-offset.mir [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
allocate-lmul-2-4-8.ll [RISCV] Fix missing emergency slots for scalable stack offsets 2021-04-20 09:59:41 +01:00
cleanup-vsetivli.mir [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
cleanup-vsetvli.mir [RISCV] Optimize more redundant VSETVLIs 2021-04-02 10:04:07 +01:00
emergency-slot.mir [RISCV] Further fixes for RVV stack offset computation 2021-04-21 10:51:07 +01:00
extload-truncstore.ll [RISCV] Expand scalable-vector truncstores and extloads 2021-04-05 17:03:45 +01:00
extract-subvector.ll [RISCV] Fix INSERT/EXTRACT_SUBVECTOR on fractional LMUL types 2021-03-01 11:51:05 +00:00
extractelt-fp-rv32.ll [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli 2021-02-25 07:51:19 -08:00
extractelt-fp-rv64.ll [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli 2021-02-25 07:51:19 -08:00
extractelt-i1.ll [RISCV] Support extract_vector_elt for fixed and scalable masked registers. 2021-03-11 09:26:44 -08:00
extractelt-int-rv32.ll [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli 2021-02-25 07:51:19 -08:00
extractelt-int-rv64.ll [RISCV] Teach CleanupVSETVLI to remove 'vsetvli zero, zero, vtype' when the vtype matches the previous vsetvli or vsetivli 2021-02-25 07:51:19 -08:00
fixed-vectors-abs.ll [RISCV] Optimize fixed vector ABS. Fix crash on scalable vector ABS for SEW=64 with RV32. 2021-03-09 08:51:03 -08:00
fixed-vectors-bitcast.ll [RISCV] Add support for bitcasts between scalars and fixed-length vectors 2021-04-05 17:21:55 +01:00
fixed-vectors-bitreverse.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-bswap.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-calling-conv.ll [RISCV] Fix stack slot for argument types (Bug 49500) 2021-04-29 09:10:48 +01:00
fixed-vectors-ctlz.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-ctpop.ll [RISCV] Optimize BUILD_VECTOR sequences that reveal hidden splats 2021-03-25 10:35:31 +00:00
fixed-vectors-cttz.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-extload-truncstore.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-extract-i1.ll [RISCV] Support extract_vector_elt for fixed and scalable masked registers. 2021-03-11 09:26:44 -08:00
fixed-vectors-extract-subvector.ll [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte. 2021-04-19 11:05:18 -07:00
fixed-vectors-extract.ll [RISCV][NFC] Merge RV32/RV64 test checks with a common prefix 2021-04-30 09:43:48 +01:00
fixed-vectors-fp-bitcast.ll [RISCV] Add support for bitcasts between scalars and fixed-length vectors 2021-04-05 17:21:55 +01:00
fixed-vectors-fp-buildvec.ll [RISCV] Match splatted load to scalar load + splat. Form strided load during isel. 2021-04-26 13:32:03 -07:00
fixed-vectors-fp-conv.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-fp-setcc.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-fp-shuffles.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-fp-splat.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-fp-vrgather.ll [RISCV] Turn splat shuffles of vector loads into strided load with stride of x0. 2021-04-22 10:02:57 -07:00
fixed-vectors-fp.ll [RISCV] Support fixed vector copysign. 2021-03-11 09:57:24 -08:00
fixed-vectors-fp2i.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-i2fp.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-insert-subvector.ll [CodeGen] Improve code generation for clamping of constant indices with scalable vectors 2021-04-19 08:34:17 +01:00
fixed-vectors-insert.ll [RISCV][NFC] Merge RV32/RV64 test checks with a common prefix 2021-04-30 09:43:48 +01:00
fixed-vectors-int-buildvec.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-int-exttrunc.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-int-setcc.ll [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates 2021-04-12 18:36:45 +01:00
fixed-vectors-int-shuffles.ll [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. 2021-04-29 08:20:09 -07:00
fixed-vectors-int-splat.ll [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. 2021-04-29 08:20:09 -07:00
fixed-vectors-int-vrgather.ll [RISCV] Turn splat shuffles of vector loads into strided load with stride of x0. 2021-04-22 10:02:57 -07:00
fixed-vectors-int.ll [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. 2021-04-29 08:20:09 -07:00
fixed-vectors-mask-buildvec.ll [RISCV] Optimize all-constant mask BUILD_VECTORs 2021-03-23 10:11:19 +00:00
fixed-vectors-mask-load-store.ll [RISCV] Pad v4i1/v2i1/v1i1 stores with 0s to make a full byte. 2021-04-19 11:05:18 -07:00
fixed-vectors-mask-logic.ll [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible. 2021-02-24 16:07:33 -08:00
fixed-vectors-mask-splat.ll [RISCV] Lower splats of non-constant i1s as SETCCs 2021-05-04 09:14:05 +01:00
fixed-vectors-masked-gather.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-masked-load-fp.ll [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register. 2021-03-29 10:20:43 -07:00
fixed-vectors-masked-load-int.ll [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. 2021-04-29 08:20:09 -07:00
fixed-vectors-masked-scatter.ll [RISCV] Correct VL for fixed length masked scatter. 2021-05-10 09:50:08 -07:00
fixed-vectors-masked-store-fp.ll [RISCV] When custom iseling masked stores, copy the mask into V0 instead of virtual register. 2021-04-05 21:28:32 -07:00
fixed-vectors-masked-store-int.ll [RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32. 2021-04-29 08:20:09 -07:00
fixed-vectors-reduction-fp.ll [RISCV] Add support for fmin/fmax vector reductions 2021-05-03 10:33:51 +01:00
fixed-vectors-reduction-int.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-select-fp.ll [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion 2021-05-10 08:22:35 +01:00
fixed-vectors-select-int.ll [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion 2021-05-10 08:22:35 +01:00
fixed-vectors-stepvector-rv32.ll [RISCV] Add support for the stepvector intrinsic 2021-03-31 11:41:17 +01:00
fixed-vectors-stepvector-rv64.ll [RISCV] Select 5 bit immediate for VSETIVLI during isel rather than peepholing in the custom inserter. 2021-04-27 14:38:16 -07:00
fixed-vectors-vadd-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
fixed-vectors-vand-vp.ll [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR 2021-05-05 12:58:08 +01:00
fixed-vectors-vdiv-vp.ll [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV 2021-05-05 13:08:57 +01:00
fixed-vectors-vdivu-vp.ll [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV 2021-05-05 13:08:57 +01:00
fixed-vectors-vfmax.ll [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max) 2021-04-23 12:22:15 +01:00
fixed-vectors-vfmin.ll [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max) 2021-04-23 12:22:15 +01:00
fixed-vectors-vmul-vp.ll [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV 2021-05-05 13:08:57 +01:00
fixed-vectors-vnsra-vnsrl.ll [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. 2021-05-11 09:29:31 -07:00
fixed-vectors-vor-vp.ll [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR 2021-05-05 12:58:08 +01:00
fixed-vectors-vreductions-mask.ll [RISCV] Support OR/XOR/AND reductions on vector masks 2021-04-08 09:46:38 +01:00
fixed-vectors-vrem-vp.ll [RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM 2021-05-05 13:13:34 +01:00
fixed-vectors-vremu-vp.ll [RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM 2021-05-05 13:13:34 +01:00
fixed-vectors-vrsub-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
fixed-vectors-vselect.ll [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible. 2021-02-24 16:07:33 -08:00
fixed-vectors-vshl-vp.ll [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR 2021-05-05 13:01:04 +01:00
fixed-vectors-vsra-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
fixed-vectors-vsrl-vp.ll [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR 2021-05-05 13:01:04 +01:00
fixed-vectors-vsub-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
fixed-vectors-vxor-vp.ll [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR 2021-05-05 12:58:08 +01:00
frameindex-addr.ll [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
inline-asm.ll [RISCV] Support inline asm for vector instructions. 2021-03-15 11:02:18 +08:00
insert-subvector.ll [RISCV] Test llvm.experimental.vector.insert intrinsics on RV32 2021-04-02 11:49:54 +01:00
insertelt-fp-rv32.ll [RISCV] Optimize INSERT_VECTOR_ELT sequences 2021-03-12 09:13:38 +00:00
insertelt-fp-rv64.ll [RISCV] Optimize INSERT_VECTOR_ELT sequences 2021-03-12 09:13:38 +00:00
insertelt-int-rv32.ll [RISCV] Optimize INSERT_VECTOR_ELT sequences 2021-03-12 09:13:38 +00:00
insertelt-int-rv64.ll [RISCV] Optimize INSERT_VECTOR_ELT sequences 2021-03-12 09:13:38 +00:00
interleave-crash.ll [RISCV] Cap legal fixed-length vectors to 256-element types 2021-05-05 09:51:08 +01:00
load-add-store-8.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-add-store-16.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-add-store-32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-add-store-64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
load-mask.ll [RISCV] Load/store vector mask types. 2021-02-03 13:44:15 +08:00
localvar.ll [RISCV] Fix StackOffset calculation when using sp to access the fixed stack object in the case of rvv vector objects existed 2021-04-30 11:02:38 +08:00
mask-exts-truncs-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
mask-exts-truncs-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
mask-reg-alloc.mir [RISCV] Improve register allocation around vector masks 2021-02-20 14:47:51 +00:00
masked-load-fp.ll [RISCV] Look through copies when trying to find an implicit def in addVSetVL. 2021-03-16 07:59:09 -07:00
masked-load-int.ll [RISCV] Look through copies when trying to find an implicit def in addVSetVL. 2021-03-16 07:59:09 -07:00
masked-store-fp.ll [RISCV] Add support for scalable vector masked load/store. 2021-03-12 10:32:33 -08:00
masked-store-int.ll [DAGCombiner] Use isConstantSplatVectorAllZeros/Ones instead of isBuildVectorAllZeros/Ones in visitMSTORE and visitMLOAD. 2021-03-12 12:14:56 -08:00
memory-args.ll change rvv frame layout 2021-03-13 16:05:55 +08:00
mgather-sdnode.ll [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register. 2021-03-29 10:20:43 -07:00
mscatter-sdnode.ll [DAGCombiner][RISCV] Teach visitMGATHER/MSCATTER to remove gather/scatters with all zeros masks that use SPLAT_VECTOR. 2021-03-18 15:34:14 -07:00
named-vector-shuffle-reverse.ll [RISCV] Add support for VECTOR_REVERSE for scalable vector types. 2021-03-09 10:03:45 -08:00
regalloc-fast-crash.ll [RISCV] When custom iseling masked loads/stores, copy the mask into V0 instead of virtual register. 2021-03-29 10:20:43 -07:00
rv32-spill-vector-csr.ll [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
rv32-spill-vector.ll change rvv frame layout 2021-03-13 16:05:55 +08:00
rv32-spill-zvlsseg.ll [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
rv32-vsetvli-intrinsics.ll [RISCV] Optimize more redundant VSETVLIs 2021-04-02 10:04:07 +01:00
rv64-spill-vector-csr.ll [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
rv64-spill-vector.ll change rvv frame layout 2021-03-13 16:05:55 +08:00
rv64-spill-zvlsseg.ll [RISCV] Spilling for Zvlsseg registers. 2021-03-19 07:46:16 +08:00
rv64-vsetvli-intrinsics.ll [RISCV] Optimize more redundant VSETVLIs 2021-04-02 10:04:07 +01:00
rvv-framelayout.ll [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
rvv-vscale.i32.ll [RISCV] Custom lower ISD::VSCALE. 2021-01-13 17:14:49 -08:00
rvv-vscale.i64.ll [RISCV] Custom lower ISD::VSCALE. 2021-01-13 17:14:49 -08:00
saddo-sdnode.ll [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates 2021-04-12 18:36:45 +01:00
select-fp.ll [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion 2021-05-10 08:22:35 +01:00
select-int.ll [LegalizeVectorOps][RISCV] Add scalable-vector SELECT expansion 2021-05-10 08:22:35 +01:00
setcc-fp-rv32.ll [RISCV] Add a pattern for a scalable vector mask vnot. 2021-02-11 15:34:58 -08:00
setcc-fp-rv64.ll [RISCV] Add a pattern for a scalable vector mask vnot. 2021-02-11 15:34:58 -08:00
setcc-integer-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
setcc-integer-rv64.ll [RISCV] Support vector SET[U]LT and SET[U]GE with splatted immediates 2021-04-12 18:36:45 +01:00
stepvector.ll [RISCV] Support STEP_VECTOR with a step greater than one 2021-04-30 09:36:18 +01:00
tail-agnostic-impdef-copy.mir [RISCV] Store SEW in RISCV vector pseudo instructions in log2 form. 2021-05-02 12:09:20 -07:00
vaadd-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vaadd-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vaaddu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vaaddu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vadc-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vadc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vadd-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vadd-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vadd-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vadd-sdnode-rv64.ll [SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR 2021-04-07 10:03:33 -07:00
vadd-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
vamoadd-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoadd-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoand-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoand-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamomax-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamomax-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamomaxu-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamomaxu-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamomin-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamomin-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamominu-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamominu-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoor-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoor-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoswap-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoswap-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vamoxor-rv32.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vamoxor-rv64.ll [RISCV] Add nxvXi64 test cases to the RV32 Zvamo intrinsic test files. NFC 2021-04-01 17:08:20 -07:00
vand-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vand-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vand-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vand-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vand-vp.ll [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR 2021-05-05 12:58:08 +01:00
vasub-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vasub-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vasubu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vasubu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vcompress-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vcompress-rv64.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vdiv-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vdiv-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vdiv-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vdiv-sdnode-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vdiv-vp.ll [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV 2021-05-05 13:08:57 +01:00
vdivu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vdivu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vdivu-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vdivu-sdnode-rv64.ll [RISCV] Fix incorrect RVV sdiv/udiv lowering 2021-02-02 18:35:53 +00:00
vdivu-vp.ll [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV 2021-05-05 13:08:57 +01:00
vexts-sdnode-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vexts-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfabs-sdnode.ll [RISCV] Add patterns for scalable-vector fabs & fcopysign 2021-02-16 10:21:09 +00:00
vfadd-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfadd-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfadd-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfclass-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfclass-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfcopysign-sdnode.ll [RISCV] Add patterns for scalable-vector fabs & fcopysign 2021-02-16 10:21:09 +00:00
vfcvt-f-x-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfcvt-f-x-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfcvt-f-xu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfcvt-f-xu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfcvt-rtz-x-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfcvt-rtz-x-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfcvt-rtz-xu-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfcvt-rtz-xu-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfcvt-x-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfcvt-x-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfcvt-xu-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfcvt-xu-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfdiv-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfdiv-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfdiv-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfirst-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfirst-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmacc-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmacc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmadd-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmadd-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmadd-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmax-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmax-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmax-sdnode.ll [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max) 2021-04-23 12:22:15 +01:00
vfmerge-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmerge-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmin-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmin-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmin-sdnode.ll [RISCV] Custom lower vector F(MIN|MAX)NUM to vf(min|max) 2021-04-23 12:22:15 +01:00
vfmsac-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmsac-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmsub-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmsub-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfmsub-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmul-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmul-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfmul-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfmv.f.s.ll [RISCV] Define different pseudo instructions for different FPR. 2021-01-26 15:48:35 +08:00
vfmv.s.f-rv32.ll [RISCV] Define different pseudo instructions for different FPR. 2021-01-26 15:48:35 +08:00
vfmv.s.f-rv64.ll [RISCV] Define different pseudo instructions for different FPR. 2021-01-26 15:48:35 +08:00
vfmv.v.f-rv32.ll [RISCV] Define different pseudo instructions for different FPR. 2021-01-26 15:48:35 +08:00
vfmv.v.f-rv64.ll [RISCV] Define different pseudo instructions for different FPR. 2021-01-26 15:48:35 +08:00
vfncvt-f-f-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-f-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-f-x-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfncvt-f-x-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-f-xu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfncvt-f-xu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-rod-f-f-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-rod-f-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-rtz-x-f-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-rtz-x-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-rtz-xu-f-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-rtz-xu-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-x-f-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-x-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-xu-f-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfncvt-xu-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfneg-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfnmacc-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmacc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmadd-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmadd-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmadd-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfnmsac-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmsac-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmsub-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmsub-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfnmsub-sdnode.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfpext-sdnode.ll [RISCV] Add support for RVV int<->fp & fp<->fp conversions 2021-01-28 09:50:32 +00:00
vfptoi-sdnode.ll [RISCV] Add support for RVV int<->fp & fp<->fp conversions 2021-01-28 09:50:32 +00:00
vfptrunc-sdnode.ll [RISCV] Add support for RVV int<->fp & fp<->fp conversions 2021-01-28 09:50:32 +00:00
vfrdiv-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfrdiv-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfrec7-rv32.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vfrec7-rv64.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vfredmax-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfredmax-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfredmin-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfredmin-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfredosum-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfredosum-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfredsum-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfredsum-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfrsqrt7-rv32.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vfrsqrt7-rv64.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vfrsub-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfrsub-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfsgnj-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfsgnj-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfsgnjn-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfsgnjn-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfsgnjx-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfsgnjx-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfslide1down-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfslide1down-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfslide1up-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfslide1up-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfsqrt-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfsqrt-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfsqrt-sdnode.ll [RISCV] Add patterns for scalable-vector fsqrt 2021-02-05 09:39:19 +00:00
vfsub-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfsub-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vfsub-sdnode.ll [RISCV] Merge rv32 and rv64 vector fadd/fsub/fmul/fdiv sdnode tests into single tests files with 2 run lines. 2021-01-29 17:32:08 -08:00
vfwadd-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwadd-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwadd.w-rv32.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vfwadd.w-rv64.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vfwcvt-f-f-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-f-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-f-x-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-f-x-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-f-xu-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-f-xu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-rtz-x-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfwcvt-rtz-x-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-rtz-xu-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfwcvt-rtz-xu-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-x-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfwcvt-x-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwcvt-xu-f-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vfwcvt-xu-f-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwmacc-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwmacc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwmsac-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwmsac-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwmul-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwmul-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwnmacc-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwnmacc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwnmsac-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwnmsac-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwredosum-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwredosum-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwredsum-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwredsum-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwsub-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwsub-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vfwsub.w-rv32.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vfwsub.w-rv64.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vid-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vid-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
viota-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
viota-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vitofp-sdnode.ll [RISCV] Add support for RVV int<->fp & fp<->fp conversions 2021-01-28 09:50:32 +00:00
vle-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vle-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vle1-rv32.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vle1-rv64.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vleff-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vleff-rv64.ll [RISCV] Add a VL output to vleff intrinsics. 2021-01-21 17:19:58 -08:00
vloxei-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vloxei-rv64.ll [RISCV] Add constraint for RVV indexed loads. 2021-03-26 07:23:24 -07:00
vloxseg-rv32.ll [RISCV] Remove redundant test cases for index segment load (1/8). 2021-02-19 11:56:08 +08:00
vloxseg-rv64.ll [RISCV] Remove redundant test cases for index segment load (2/8). 2021-02-19 11:56:08 +08:00
vlse-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vlse-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vlseg-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vlseg-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vlsegff-rv32-dead.ll [RISCV] Implement vlsegff intrinsics. 2021-01-26 12:02:43 +08:00
vlsegff-rv32.ll [RISCV] Implement vlsegff intrinsics. 2021-01-26 12:02:43 +08:00
vlsegff-rv64-dead.ll [RISCV] Implement vlsegff intrinsics. 2021-01-26 12:02:43 +08:00
vlsegff-rv64.ll [RISCV] Implement vlsegff intrinsics. 2021-01-26 12:02:43 +08:00
vlsseg-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vlsseg-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vluxei-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vluxei-rv64.ll [RISCV] Add constraint for RVV indexed loads. 2021-03-26 07:23:24 -07:00
vluxseg-rv32.ll [RISCV] Remove redundant test cases for index segment load (3/8). 2021-02-19 11:56:08 +08:00
vluxseg-rv64.ll [RISCV] Remove redundant test cases for index segment load (4/8). 2021-02-19 11:56:08 +08:00
vmacc-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmacc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmadc-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmadc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmadc.carry.in-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmadc.carry.in-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmadd-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmadd-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmand-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmand-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmandnot-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmandnot-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmarith-sdnode.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmax-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmax-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vmax-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmax-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmaxu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmaxu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vmaxu-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmaxu-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmclr-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmclr-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmerge-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmerge-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmfeq-rv32.ll [RISCV] Add missing nxvXf64 intrinsics tests cases for floating-point compare for RV32. 2021-04-01 20:57:13 -07:00
vmfeq-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmfge-rv32.ll [RISCV] Support vector type for second operand of vmfge and vmfgt IR intrinsics. 2021-04-22 10:44:38 -07:00
vmfge-rv64.ll [RISCV] Support vector type for second operand of vmfge and vmfgt IR intrinsics. 2021-04-22 10:44:38 -07:00
vmfgt-rv32.ll [RISCV] Support vector type for second operand of vmfge and vmfgt IR intrinsics. 2021-04-22 10:44:38 -07:00
vmfgt-rv64.ll [RISCV] Support vector type for second operand of vmfge and vmfgt IR intrinsics. 2021-04-22 10:44:38 -07:00
vmfle-rv32.ll [RISCV] Add missing nxvXf64 intrinsics tests cases for floating-point compare for RV32. 2021-04-01 20:57:13 -07:00
vmfle-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmflt-rv32.ll [RISCV] Add missing nxvXf64 intrinsics tests cases for floating-point compare for RV32. 2021-04-01 20:57:13 -07:00
vmflt-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmfne-rv32.ll [RISCV] Add missing nxvXf64 intrinsics tests cases for floating-point compare for RV32. 2021-04-01 20:57:13 -07:00
vmfne-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmin-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmin-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vmin-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmin-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vminu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vminu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vminu-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vminu-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmnand-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmnand-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmnor-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmnor-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmor-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmor-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmornot-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmornot-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsbc-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmsbc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsbc.borrow.in-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmsbc.borrow.in-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsbf-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsbf-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmseq-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmseq-rv64.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vmset-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmset-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsge-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsge-rv64.ll [RISCV] Add IR intrinsics for vmsge(u).vv/vx/vi. 2021-04-22 10:44:38 -07:00
vmsgeu-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsgeu-rv64.ll [RISCV] Add IR intrinsics for vmsge(u).vv/vx/vi. 2021-04-22 10:44:38 -07:00
vmsgt-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsgt-rv64.ll [RISCV] Add missing tests for vector type for second operand of vmsgt and vmsgtu IR intrinsics. 2021-04-22 10:44:38 -07:00
vmsgtu-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsgtu-rv64.ll [RISCV] Add missing tests for vector type for second operand of vmsgt and vmsgtu IR intrinsics. 2021-04-22 10:44:38 -07:00
vmsif-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsif-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsle-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsle-rv64.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vmsleu-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsleu-rv64.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vmslt-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmslt-rv64.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vmsltu-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsltu-rv64.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vmsne-rv32.ll [RISCV] Remove GetVRegNoV0 from the output register class of masked compare pseudo instructions. 2021-04-23 09:33:29 -07:00
vmsne-rv64.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vmsof-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmsof-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmul-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmul-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vmul-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vmul-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmul-vp.ll [RISCV][VP][NFC] Add tests for VP_MUL and VP_[US]DIV 2021-05-05 13:08:57 +01:00
vmulh-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmulh-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vmulh-sdnode-rv32.ll [SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR 2021-04-07 10:03:33 -07:00
vmulhsu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmulhsu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vmulhu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmulhu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vmv.s.x-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmv.s.x-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmv.v.v-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmv.v.v-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmv.v.x-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vmv.v.x-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmv.x.s-rv32.ll [RISCV] Handle vmv.x.s intrinsic for i64 vectors on RV32. 2021-03-11 09:39:50 -08:00
vmv.x.s-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmxnor-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmxnor-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmxor-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vmxor-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vnclip-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vnclip-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vnclipu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vnclipu-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vnmsac-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vnmsac-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vnmsub-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vnmsub-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vnsra-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vnsra-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vnsrl-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vnsrl-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vor-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vor-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vor-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vor-sdnode-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vor-vp.ll [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR 2021-05-05 12:58:08 +01:00
vpopc-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vpopc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vredand-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredand-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vredmax-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredmax-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vredmaxu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredmaxu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vredmin-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredmin-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vredminu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredminu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vredor-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredor-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vredsum-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredsum-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vreductions-fp-sdnode.ll [RISCV] Add support for fmin/fmax vector reductions 2021-05-03 10:33:51 +01:00
vreductions-int-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vreductions-int-rv64.ll [RISCV] Improve 64-bit integer materialization for some cases. 2021-04-01 09:12:52 -07:00
vreductions-mask.ll [RISCV] Support OR/XOR/AND reductions on vector masks 2021-04-08 09:46:38 +01:00
vredxor-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vredxor-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vrem-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vrem-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vrem-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vrem-sdnode-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vrem-vp.ll [RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM 2021-05-05 13:13:34 +01:00
vremu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vremu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vremu-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vremu-sdnode-rv64.ll [SelectionDAG] Support scalable-vector splats in more cases 2021-01-25 10:58:15 +00:00
vremu-vp.ll [RISCV][VP][NFC] Add tests for VP_SREM and VP_UREM 2021-05-05 13:13:34 +01:00
vrgather-rv32.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vrgather-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vrgatherei16-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vrgatherei16-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vrsub-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vrsub-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vrsub-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vrsub-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vrsub-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
vsadd-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vsadd-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vsaddu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vsaddu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vsbc-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vsbc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vse-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vse-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vse1-rv32.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vse1-rv64.ll [RISCV] Add new vector instructions in v0.10. 2021-02-03 13:28:58 +08:00
vselect-fp-rv32.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vselect-fp-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vselect-int-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vselect-int-rv64.ll [DAGCombiner] Support all-ones/all-zeros SPLAT_VECTOR in more combines 2021-04-21 11:05:37 +01:00
vsetvl-ext.ll [RISCV] Teach computeKnownBits that vsetvli returns number less than 2^31. 2021-04-29 08:07:59 -07:00
vsext-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vsext-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vshl-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vshl-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vshl-vp.ll [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR 2021-05-05 13:01:04 +01:00
vslide1down-rv32.ll [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32. 2021-04-07 10:44:53 -07:00
vslide1down-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vslide1up-rv32.ll [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32. 2021-04-07 10:44:53 -07:00
vslide1up-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vslidedown-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vslidedown-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vslideup-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vslideup-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsll-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vsll-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vsmul-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vsmul-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vsoxei-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vsoxei-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsoxseg-rv32.ll [RISCV] Remove redundant test cases for index segment store (5/8). 2021-02-19 11:56:08 +08:00
vsoxseg-rv64.ll [RISCV] Remove redundant test cases for index segment store (6/8). 2021-02-19 11:56:08 +08:00
vsplats-fp.ll [RISCV] Adjust RISCVInstrInfoVSDPatterns.td for different pseudo instructions for different FPR. 2021-01-26 01:00:50 -08:00
vsplats-i1.ll [RISCV] Lower splats of non-constant i1s as SETCCs 2021-05-04 09:14:05 +01:00
vsplats-i64.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vsra-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vsra-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vsra-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vsra-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsra-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
vsrl-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vsrl-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vsrl-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vsrl-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsrl-vp.ll [RISCV][VP][NFC] Add tests for VP_SHL and VP_LSHR 2021-05-05 13:01:04 +01:00
vsse-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vsse-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsseg-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsseg-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vssra-rv32.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vssra-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vssrl-rv32.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vssrl-rv64.ll [RISCV] Update RVV shift intrinsic tests to use XLEN bit as shift amount. 2021-03-17 10:47:49 -07:00
vssseg-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vssseg-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vssub-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vssub-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vssubu-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vssubu-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vsub-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vsub-rv64.ll [RISCV] Add isel patterns to select vsub_vx intrinsic to vadd.vi if it uses a small enough immediate 2021-03-31 09:26:41 -07:00
vsub-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vsub-sdnode-rv64.ll [SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR 2021-04-07 10:03:33 -07:00
vsub-vp.ll [RISCV][VP] Lower VP ISD nodes to RVV instructions 2021-05-05 12:32:24 +01:00
vsuxei-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vsuxei-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vsuxseg-rv32.ll [RISCV] Remove redundant test cases for index segment store (7/8). 2021-02-19 11:56:08 +08:00
vsuxseg-rv64.ll [RISCV] Remove redundant test cases for index segment store (8/8). 2021-02-19 11:56:08 +08:00
vtruncs-sdnode-rv32.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vtruncs-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwadd-rv32.ll [RISCV] Starting fixing issues that prevent us from testing vXi64 intrinsics on RV32. 2021-03-10 09:45:38 -08:00
vwadd-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwadd.w-rv32.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vwadd.w-rv64.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vwaddu-rv32.ll [RISCV] Starting fixing issues that prevent us from testing vXi64 intrinsics on RV32. 2021-03-10 09:45:38 -08:00
vwaddu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwaddu.w-rv32.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vwaddu.w-rv64.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vwmacc-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwmacc-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwmaccsu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwmaccsu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwmaccu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwmaccu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwmaccus-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwmaccus-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwmul-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwmul-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwmulsu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwmulsu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwmulu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwmulu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwredsum-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwredsum-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwredsumu-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vwredsumu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwsub-rv32.ll [RISCV] Starting fixing issues that prevent us from testing vXi64 intrinsics on RV32. 2021-03-10 09:45:38 -08:00
vwsub-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwsub.w-rv32.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vwsub.w-rv64.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vwsubu-rv32.ll [RISCV] Starting fixing issues that prevent us from testing vXi64 intrinsics on RV32. 2021-03-10 09:45:38 -08:00
vwsubu-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vwsubu.w-rv32.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vwsubu.w-rv64.ll [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf. 2021-04-11 10:19:45 -07:00
vxor-rv32.ll [RISCV] Use stack temporary to splat two GPRs into SEW=64 vector on RV32. 2021-04-22 09:50:07 -07:00
vxor-rv64.ll [RISCV] Use whole register load/store for generic load/store. 2021-02-09 15:52:04 +08:00
vxor-sdnode-rv32.ll [RISCV] Use stack slot to handle SPLAT_VECTOR_PARTS on RV32. 2021-04-26 15:43:02 -07:00
vxor-sdnode-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
vxor-vp.ll [RISCV][VP][NFC] Add tests for VP_AND, VP_XOR, VP_OR 2021-05-05 12:58:08 +01:00
vzext-rv32.ll [RISCV] Add more nxvi64 vector intrinsic tests for RV32. NFC 2021-04-01 20:34:28 -07:00
vzext-rv64.ll [RISCV] Use v8-v23 as argument registers to conform to the proposal. 2021-01-22 07:55:24 +08:00
wrong-stack-slot-rv32.mir [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
wrong-stack-slot-rv64.mir [RISCV] Fix offset computation for RVV 2021-03-29 17:03:49 +00:00
zvlsseg-copy.mir [RISCV] Implement COPY for Zvlsseg registers 2021-04-13 18:55:51 -07:00
zvlsseg-spill.mir [RISCV] Fix the calculation of the offset of Zvlsseg spilling. 2021-05-11 10:13:18 +08:00
zvlsseg-zero-vl.ll [RISCV] Teach VSETVLI inserter to use VSETIVLI when possible. 2021-02-24 16:07:33 -08:00