llvm-project/llvm/test/CodeGen
Roman Lebedev 5f78ba001c
[X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32)
I've seen this in the RawSpeed's BitPumpMSB*::push() hotpath,
after fixing the buffer abstraction to a more sane one,
when looking into a +5% runtime regression.
I was hoping that this would fix it, but it does not look it does.

This seems to be at least not worse than the original pattern.
But i'm actually mainly interested in the case where we already
compute `(y+32)` (see last test),

https://alive2.llvm.org/ce/z/ZCzJio

Reviewed By: spatel

Differential Revision: https://reviews.llvm.org/D101944
2021-05-11 19:39:41 +03:00
..
AArch64 [AArch64][GlobalISel] Add post-legalizer lowering for NEON vector fcmps 2021-05-10 15:40:06 -07:00
AMDGPU [AMDGPU] Move code sinking before structurizer 2021-05-11 14:07:23 +02:00
ARC
ARM [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-10 12:35:11 -07:00
AVR
BPF BPF: fix FIELD_EXISTS relocation with array subscripts 2021-05-06 22:37:02 -07:00
Generic [VecLib] Add support for vector fns from Darwin's libsystem. 2021-05-10 21:19:58 +01:00
Hexagon [Hexagon] Handle loads and stores of scalar predicate vectors 2021-05-10 16:42:22 -05:00
Inputs
Lanai
M68k [M68k][AsmParser] Fix invalid register name parsing logics 2021-05-05 17:13:02 -07:00
MIR [AMDGPU] Serialize MFInfo::ScavengeFI 2021-05-07 11:15:25 +02:00
MSP430
Mips [SelectionDAG][Mips][PowerPC][RISCV][WebAssembly] Teach computeKnownBits/ComputeNumSignBits about atomics 2021-05-06 04:01:20 +01:00
NVPTX [NVPTX] Enable lowering of atomics on local memory 2021-04-26 20:12:12 -04:00
PowerPC [PowerPC][Bug] Fix Bug in Stack Frame Update Code 2021-05-11 05:54:07 -05:00
RISCV [RISCV] Match trunc_vector_vl+sra_vl/srl_vl with splat shift amount to vnsra/vnsrl. 2021-05-11 09:29:31 -07:00
SPARC [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-10 12:35:11 -07:00
SystemZ [TargetLowering] Only inspect attributes in the arguments for ArgListEntry 2021-05-10 12:35:11 -07:00
Thumb Support {S,U}REMEqFold before legalization 2021-04-01 01:35:41 +03:00
Thumb2 [ARM] Transforming memset to Tail predicated Loop 2021-05-07 13:35:53 +01:00
VE
WebAssembly [CodeGen][WebAssembly] Better lowering for WASM_SYMBOL_TYPE_GLOBAL symbols 2021-05-11 11:47:40 +02:00
WinCFGuard
WinEH
X86 [X86][Codegen] Shift amount mod: sh? i64 x, (32-y) --> sh? i64 x, -(y+32) 2021-05-11 19:39:41 +03:00
XCore