forked from OSchip/llvm-project
324 lines
12 KiB
TableGen
324 lines
12 KiB
TableGen
//===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the target-independent interfaces which should be
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// implemented by each target which is using a TableGen based code generator.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Value types - These values correspond to the register types defined in the
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// ValueTypes.h file. If you update anything here, you must update it there as
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// well!
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//
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class ValueType<int size, int value> {
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string Namespace = "MVT";
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int Size = size;
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int Value = value;
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}
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def OtherVT: ValueType<0 , 0>; // "Other" value
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def i1 : ValueType<1 , 1>; // One bit boolean value
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def i8 : ValueType<8 , 2>; // 8-bit integer value
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def i16 : ValueType<16 , 3>; // 16-bit integer value
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def i32 : ValueType<32 , 4>; // 32-bit integer value
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def i64 : ValueType<64 , 5>; // 64-bit integer value
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def i128 : ValueType<128, 6>; // 128-bit integer value
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def f32 : ValueType<32 , 7>; // 32-bit floating point value
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def f64 : ValueType<64 , 8>; // 64-bit floating point value
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def f80 : ValueType<80 , 9>; // 80-bit floating point value
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def f128 : ValueType<128, 10>; // 128-bit floating point value
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def FlagVT : ValueType<0 , 11>; // Condition code or machine flag
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def isVoid : ValueType<0 , 12>; // Produces no value
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def Vector : ValueType<0 , 13>; // Abstract vector value
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def v16i8 : ValueType<128, 14>; // 16 x i8 vector value
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def v8i16 : ValueType<128, 15>; // 8 x i16 vector value
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def v4i32 : ValueType<128, 16>; // 4 x i32 vector value
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def v2i64 : ValueType<128, 17>; // 2 x i64 vector value
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def v4f32 : ValueType<128, 18>; // 4 x f32 vector value
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def v2f64 : ValueType<128, 19>; // 2 x f64 vector value
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//===----------------------------------------------------------------------===//
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// Register file description - These classes are used to fill in the target
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// description classes.
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class RegisterClass; // Forward def
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// Register - You should define one instance of this class for each register
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// in the target machine. String n will become the "name" of the register.
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class Register<string n> {
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string Namespace = "";
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string Name = n;
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// SpillSize - If this value is set to a non-zero value, it is the size in
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// bits of the spill slot required to hold this register. If this value is
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// set to zero, the information is inferred from any register classes the
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// register belongs to.
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int SpillSize = 0;
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// SpillAlignment - This value is used to specify the alignment required for
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// spilling the register. Like SpillSize, this should only be explicitly
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// specified if the register is not in a register class.
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int SpillAlignment = 0;
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// Aliases - A list of registers that this register overlaps with. A read or
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// modification of this register can potentially read or modifie the aliased
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// registers.
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//
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list<Register> Aliases = [];
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}
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// RegisterGroup - This can be used to define instances of Register which
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// need to specify aliases.
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// List "aliases" specifies which registers are aliased to this one. This
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// allows the code generator to be careful not to put two values with
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// overlapping live ranges into registers which alias.
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class RegisterGroup<string n, list<Register> aliases> : Register<n> {
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let Aliases = aliases;
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}
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// RegisterClass - Now that all of the registers are defined, and aliases
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// between registers are defined, specify which registers belong to which
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// register classes. This also defines the default allocation order of
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// registers by register allocators.
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//
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class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
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list<Register> regList> {
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string Namespace = namespace;
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// RegType - Specify the ValueType of the registers in this register class.
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// Note that all registers in a register class must have the same ValueType.
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//
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list<ValueType> RegTypes = regTypes;
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// Size - Specify the spill size in bits of the registers. A default value of
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// zero lets tablgen pick an appropriate size.
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int Size = 0;
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// Alignment - Specify the alignment required of the registers when they are
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// stored or loaded to memory.
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//
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int Alignment = alignment;
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// MemberList - Specify which registers are in this class. If the
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// allocation_order_* method are not specified, this also defines the order of
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// allocation used by the register allocator.
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//
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list<Register> MemberList = regList;
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// MethodProtos/MethodBodies - These members can be used to insert arbitrary
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// code into a generated register class. The normal usage of this is to
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// overload virtual methods.
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code MethodProtos = [{}];
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code MethodBodies = [{}];
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}
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//===----------------------------------------------------------------------===//
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// Pull in the common support for scheduling
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//
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include "../TargetSchedule.td"
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class Predicate; // Forward def
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//===----------------------------------------------------------------------===//
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// Instruction set description - These classes correspond to the C++ classes in
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// the Target/TargetInstrInfo.h file.
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//
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class Instruction {
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string Name = ""; // The opcode string for this instruction
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string Namespace = "";
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dag OperandList; // An dag containing the MI operand list.
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string AsmString = ""; // The .s format to print the instruction with.
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// Pattern - Set to the DAG pattern for this instruction, if we know of one,
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// otherwise, uninitialized.
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list<dag> Pattern;
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// The follow state will eventually be inferred automatically from the
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// instruction pattern.
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list<Register> Uses = []; // Default to using no non-operand registers
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list<Register> Defs = []; // Default to modifying no non-operand registers
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// Predicates - List of predicates which will be turned into isel matching
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// code.
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list<Predicate> Predicates = [];
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// These bits capture information about the high-level semantics of the
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// instruction.
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bit isReturn = 0; // Is this instruction a return instruction?
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bit isBranch = 0; // Is this instruction a branch instruction?
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bit isBarrier = 0; // Can control flow fall through this instruction?
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bit isCall = 0; // Is this instruction a call instruction?
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bit isLoad = 0; // Is this instruction a load instruction?
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bit isStore = 0; // Is this instruction a store instruction?
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bit isTwoAddress = 0; // Is this a two address instruction?
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bit isConvertibleToThreeAddress = 0; // Can this 2-addr instruction promote?
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bit isCommutable = 0; // Is this 3 operand instruction commutable?
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bit isTerminator = 0; // Is this part of the terminator for a basic block?
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bit hasDelaySlot = 0; // Does this instruction have an delay slot?
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bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
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bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
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InstrItinClass Itinerary; // Execution steps used for scheduling.
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}
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/// Predicates - These are extra conditionals which are turned into instruction
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/// selector matching code. Currently each predicate is just a string.
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class Predicate<string cond> {
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string CondString = cond;
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}
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class Requires<list<Predicate> preds> {
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list<Predicate> Predicates = preds;
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}
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/// ops definition - This is just a simple marker used to identify the operands
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/// list for an instruction. This should be used like this:
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/// (ops R32:$dst, R32:$src) or something similar.
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def ops;
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/// variable_ops definition - Mark this instruction as taking a variable number
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/// of operands.
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def variable_ops;
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/// Operand Types - These provide the built-in operand types that may be used
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/// by a target. Targets can optionally provide their own operand types as
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/// needed, though this should not be needed for RISC targets.
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class Operand<ValueType ty> {
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ValueType Type = ty;
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string PrintMethod = "printOperand";
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int NumMIOperands = 1;
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dag MIOperandInfo = (ops);
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}
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def i1imm : Operand<i1>;
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def i8imm : Operand<i8>;
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def i16imm : Operand<i16>;
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def i32imm : Operand<i32>;
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def i64imm : Operand<i64>;
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// InstrInfo - This class should only be instantiated once to provide parameters
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// which are global to the the target machine.
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//
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class InstrInfo {
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Instruction PHIInst;
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// If the target wants to associate some target-specific information with each
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// instruction, it should provide these two lists to indicate how to assemble
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// the target specific information into the 32 bits available.
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//
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list<string> TSFlagsFields = [];
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list<int> TSFlagsShifts = [];
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// Target can specify its instructions in either big or little-endian formats.
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// For instance, while both Sparc and PowerPC are big-endian platforms, the
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// Sparc manual specifies its instructions in the format [31..0] (big), while
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// PowerPC specifies them using the format [0..31] (little).
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bit isLittleEndianEncoding = 0;
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}
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//===----------------------------------------------------------------------===//
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// AsmWriter - This class can be implemented by targets that need to customize
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// the format of the .s file writer.
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//
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// Subtargets can have multiple different asmwriters (e.g. AT&T vs Intel syntax
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// on X86 for example).
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//
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class AsmWriter {
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// AsmWriterClassName - This specifies the suffix to use for the asmwriter
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// class. Generated AsmWriter classes are always prefixed with the target
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// name.
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string AsmWriterClassName = "AsmPrinter";
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// InstFormatName - AsmWriters can specify the name of the format string to
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// print instructions with.
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string InstFormatName = "AsmString";
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// Variant - AsmWriters can be of multiple different variants. Variants are
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// used to support targets that need to emit assembly code in ways that are
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// mostly the same for different targets, but have minor differences in
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// syntax. If the asmstring contains {|} characters in them, this integer
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// will specify which alternative to use. For example "{x|y|z}" with Variant
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// == 1, will expand to "y".
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int Variant = 0;
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}
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def DefaultAsmWriter : AsmWriter;
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//===----------------------------------------------------------------------===//
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// Target - This class contains the "global" target information
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//
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class Target {
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// CalleeSavedRegisters - As you might guess, this is a list of the callee
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// saved registers for a target.
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list<Register> CalleeSavedRegisters = [];
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// PointerType - Specify the value type to be used to represent pointers in
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// this target. Typically this is an i32 or i64 type.
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ValueType PointerType;
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// InstructionSet - Instruction set description for this target.
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InstrInfo InstructionSet;
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// AssemblyWriters - The AsmWriter instances available for this target.
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list<AsmWriter> AssemblyWriters = [DefaultAsmWriter];
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}
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//===----------------------------------------------------------------------===//
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// SubtargetFeature - A characteristic of the chip set.
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//
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class SubtargetFeature<string n, string t, string a, string d> {
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// Name - Feature name. Used by command line (-mattr=) to determine the
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// appropriate target chip.
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//
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string Name = n;
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// Type - Type of attribute to be set by feature.
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//
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string Type = t;
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// Attribute - Attribute to be set by feature.
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//
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string Attribute = a;
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// Desc - Feature description. Used by command line (-mattr=) to display help
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// information.
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//
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string Desc = d;
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}
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//===----------------------------------------------------------------------===//
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// Processor chip sets - These values represent each of the chip sets supported
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// by the scheduler. Each Processor definition requires corresponding
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// instruction itineraries.
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//
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class Processor<string n, ProcessorItineraries pi, list<SubtargetFeature> f> {
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// Name - Chip set name. Used by command line (-mcpu=) to determine the
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// appropriate target chip.
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//
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string Name = n;
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// ProcItin - The scheduling information for the target processor.
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//
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ProcessorItineraries ProcItin = pi;
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// Features - list of
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list<SubtargetFeature> Features = f;
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}
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//===----------------------------------------------------------------------===//
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// Pull in the common support for DAG isel generation
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//
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include "../TargetSelectionDAG.td"
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