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llvm-project/llvm/test/CodeGen/MIR
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Aditya Nandakumar cc6b853901 [MIRNamer]: Make the check lines in the test robust with regex. 
Previously we were checking for specific hashes. Make it check for
regexes.

Should fix failure caused by: 7276868556
 		2019-11-16 22:58:45 -08:00
..
AArch64 [MIRNamer]: Make the check lines in the test robust with regex. 2019-11-16 22:58:45 -08:00
AMDGPU [MIRNamer]: Make the check lines in the test robust with regex. 2019-11-16 22:58:45 -08:00
ARM
…
Generic [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir parsing 2019-09-11 11:16:48 +00:00
Hexagon [DebugInfo] Allow bundled calls in the MIR's call site info 2019-08-19 12:41:22 +00:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
…
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 [MIR] Add MIR parsing for heap alloc site instruction markers 2019-11-05 12:57:45 -08:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.