forked from OSchip/llvm-project
122 lines
4.8 KiB
C++
122 lines
4.8 KiB
C++
#ifndef HEXAGONVLIWPACKETIZER_H
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#define HEXAGONVLIWPACKETIZER_H
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#include "llvm/CodeGen/DFAPacketizer.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/ScheduleDAGInstrs.h"
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namespace llvm {
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class HexagonInstrInfo;
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class HexagonRegisterInfo;
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class HexagonPacketizerList : public VLIWPacketizerList {
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// Vector of instructions assigned to the packet that has just been created.
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std::vector<MachineInstr*> OldPacketMIs;
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// Has the instruction been promoted to a dot-new instruction.
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bool PromotedToDotNew;
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// Has the instruction been glued to allocframe.
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bool GlueAllocframeStore;
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// Has the feeder instruction been glued to new value jump.
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bool GlueToNewValueJump;
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// Check if there is a dependence between some instruction already in this
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// packet and this instruction.
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bool Dependence;
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// Only check for dependence if there are resources available to
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// schedule this instruction.
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bool FoundSequentialDependence;
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// Track MIs with ignored dependence.
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std::vector<MachineInstr*> IgnoreDepMIs;
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protected:
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/// \brief A handle to the branch probability pass.
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const MachineBranchProbabilityInfo *MBPI;
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const MachineLoopInfo *MLI;
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private:
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const HexagonInstrInfo *HII;
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const HexagonRegisterInfo *HRI;
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public:
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// Ctor.
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HexagonPacketizerList(MachineFunction &MF, MachineLoopInfo &MLI,
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AliasAnalysis *AA,
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const MachineBranchProbabilityInfo *MBPI);
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// initPacketizerState - initialize some internal flags.
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void initPacketizerState() override;
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// ignorePseudoInstruction - Ignore bundling of pseudo instructions.
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bool ignorePseudoInstruction(const MachineInstr &MI,
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const MachineBasicBlock *MBB) override;
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// isSoloInstruction - return true if instruction MI can not be packetized
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// with any other instruction, which means that MI itself is a packet.
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bool isSoloInstruction(const MachineInstr &MI) override;
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// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
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// together.
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bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
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// isLegalToPruneDependencies - Is it legal to prune dependece between SUI
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// and SUJ.
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bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
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MachineBasicBlock::iterator addToPacket(MachineInstr &MI) override;
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void endPacket(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI) override;
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bool shouldAddToPacket(const MachineInstr &MI) override;
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void unpacketizeSoloInstrs(MachineFunction &MF);
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protected:
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bool isCallDependent(const MachineInstr &MI, SDep::Kind DepType,
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unsigned DepReg);
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bool promoteToDotCur(MachineInstr &MI, SDep::Kind DepType,
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MachineBasicBlock::iterator &MII,
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const TargetRegisterClass *RC);
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bool canPromoteToDotCur(const MachineInstr &MI, const SUnit *PacketSU,
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unsigned DepReg, MachineBasicBlock::iterator &MII,
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const TargetRegisterClass *RC);
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void cleanUpDotCur();
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bool promoteToDotNew(MachineInstr &MI, SDep::Kind DepType,
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MachineBasicBlock::iterator &MII,
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const TargetRegisterClass *RC);
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bool canPromoteToDotNew(const MachineInstr &MI, const SUnit *PacketSU,
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unsigned DepReg, MachineBasicBlock::iterator &MII,
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const TargetRegisterClass *RC);
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bool canPromoteToNewValue(const MachineInstr &MI, const SUnit *PacketSU,
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unsigned DepReg, MachineBasicBlock::iterator &MII);
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bool canPromoteToNewValueStore(const MachineInstr &MI,
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const MachineInstr &PacketMI, unsigned DepReg);
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bool demoteToDotOld(MachineInstr &MI);
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bool useCallersSP(MachineInstr &MI);
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void useCalleesSP(MachineInstr &MI);
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bool arePredicatesComplements(MachineInstr &MI1, MachineInstr &MI2);
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bool restrictingDepExistInPacket(MachineInstr&, unsigned);
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bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
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bool isCurifiable(MachineInstr &MI);
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bool cannotCoexist(const MachineInstr &MI, const MachineInstr &MJ);
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inline bool isPromotedToDotNew() const {
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return PromotedToDotNew;
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}
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bool tryAllocateResourcesForConstExt(bool Reserve);
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bool canReserveResourcesForConstExt();
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void reserveResourcesForConstExt();
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bool hasDeadDependence(const MachineInstr &I, const MachineInstr &J);
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bool hasControlDependence(const MachineInstr &I, const MachineInstr &J);
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bool hasRegMaskDependence(const MachineInstr &I, const MachineInstr &J);
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bool hasV4SpecificDependence(const MachineInstr &I, const MachineInstr &J);
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bool producesStall(const MachineInstr &MI);
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};
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} // namespace llvm
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#endif // HEXAGONVLIWPACKETIZER_H
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