Venkatraman Govindaraju 0776cc0acd [SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI. ... Also, pass fp128 arguments to varargs through integer registers if necessary. llvm-svn: 198145		2013-12-29 01:20:36 +00:00
..
AArch64	[AArch64]Fix a problem that the register order of fmls/fmla by element is incorrect.	2013-12-25 07:12:34 +00:00
ARM	New machine model for cortex-a9. Schedule for resources and latency.	2013-12-28 21:57:05 +00:00
CPP	Begin adding docs and IR-level support for the inalloca attribute	2013-12-19 02:14:12 +00:00
Generic	Fix pr18235.	2013-12-13 16:05:32 +00:00
Hexagon	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
Inputs	Debug Info: update testing cases to specify the debug info version number.	2013-11-22 21:49:45 +00:00
MSP430	Make sure SP is always aligned on a 2 byte boundary	2013-10-24 09:32:31 +00:00
Mips	[Mips] Does not take in account 'use-soft-float' attribute's value when	2013-12-25 17:00:27 +00:00
NVPTX	[NVPTX] Fix off-by-one error when creating the VT list for an SDNode	2013-12-05 12:58:00 +00:00
PowerPC	Implement initial-exec TLS for PPC32.	2013-12-20 18:08:54 +00:00
R600	R600: Allow ftrunc	2013-12-20 05:11:55 +00:00
SPARC	[SparcV9]: Implement lowering of long double (fp128) arguments in Sparc64 ABI.	2013-12-29 01:20:36 +00:00
SystemZ	[SystemZ] Use interlocked-access 1 instructions for CodeGen	2013-12-24 15:18:04 +00:00
Thumb	Correctly handle the degenerated triple "thumb".	2013-12-18 21:29:44 +00:00
Thumb2	Enabling thumb2 mode used to force support for armv6t2. Replace this	2013-12-13 11:16:00 +00:00
X86	llvm/test/CodeGen/X86/vselect.ll: Unbreak Windows x64 targets to add -mtriple=x86_64-unknown-unknown.	2013-12-28 13:04:29 +00:00
XCore	XCore target: Make handling of large frames not dependent upon an FP.	2013-12-02 11:05:28 +00:00