llvm-project/llvm
Sam Elliott 9f155bc6e5 [RISCV] Prevent re-ordering some adds after shifts
Summary:
DAGCombine will normally turn a `(shl (add x, c1), c2)` into `(add (shl x, c2), c1 << c2)`, where `c1` and `c2` are constants. This can be prevented by a callback in TargetLowering.

On RISC-V, materialising the constant `c1 << c2` can be more expensive than materialising `c1`, because materialising the former may take more instructions, and may use a register, where materialising the latter would not.

This patch implements the hook in RISCVTargetLowering to prevent this transform, in the cases where:
- `c1` fits into the immediate field in an `addi` instruction.
- `c1` takes fewer instructions to materialise than `c1 << c2`.

In future, DAGCombine could do the check to see whether `c1` fits into an add immediate, which might simplify more targets hooks than just RISC-V.

Reviewers: asb, luismarques, efriedma

Reviewed By: asb

Subscribers: xbolva00, lebedev.ri, craig.topper, lewis-revill, Jim, hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62857

llvm-svn: 363736
2019-06-18 20:38:08 +00:00
..
benchmarks
bindings [bindings/go][NFC] Format code with go fmt 2019-06-12 11:59:09 +00:00
cmake build: extract LLVM distribution target handling 2019-06-14 18:28:57 +00:00
docs [SVE][IR] Scalable Vector IR Type with pr42210 fix 2019-06-18 10:11:56 +00:00
examples
include [PDB] Ignore .debug$S subsections with high bit set 2019-06-18 19:41:25 +00:00
lib [RISCV] Prevent re-ordering some adds after shifts 2019-06-18 20:38:08 +00:00
projects
resources
runtimes Setup testing target dependencies for default runtimes 2019-06-11 00:25:57 +00:00
test [RISCV] Prevent re-ordering some adds after shifts 2019-06-18 20:38:08 +00:00
tools [PDB] Ignore .debug$S subsections with high bit set 2019-06-18 19:41:25 +00:00
unittests [SVE][IR] Scalable Vector IR Type with pr42210 fix 2019-06-18 10:11:56 +00:00
utils Fix some lit test ResourceWarnings on Windows 2019-06-18 16:36:57 +00:00
.arcconfig
.clang-format
.clang-tidy
.gitattributes
.gitignore gitignore: Ignore Qt Creator project configuration files. NFC 2019-06-12 08:28:31 +00:00
CMakeLists.txt build: extract LLVM distribution target handling 2019-06-14 18:28:57 +00:00
CODE_OWNERS.TXT
CREDITS.TXT [test commit] Add my name to the CREDITS.TXT 2019-05-27 07:48:28 +00:00
LICENSE.TXT
LLVMBuild.txt
README.txt
RELEASE_TESTERS.TXT
configure
llvm.spec.in

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