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llvm-project/llvm/test/Transforms/SLPVectorizer
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Simon Pilgrim 9d3ef8ee2b [SLPVectorizer] Support alternate opcodes in tryToVectorizeList 
Enable tryToVectorizeList to support InstructionsState alternate opcode patterns at a root (build vector etc.) as well as further down the vectorization tree.

NOTE: This patch reduces some of the debug reporting if there are opcode mismatches - I can try to add it back if it proves a problem. But it could get rather messy trying to provide equivalent verbose debug strings via getSameOpcode etc.

Differential Revision: https://reviews.llvm.org/D48488

llvm-svn: 335364
 		2018-06-22 16:37:34 +00:00
..
AArch64 [SLPVectorizer] Relax alternate opcodes to accept any BinaryOperator pair 2018-06-22 14:04:06 +00:00
AMDGPU [SLP] Add testcases of min/max reduction pattern for AMDGPU. 2018-06-11 20:29:31 +00:00
ARM [SLPVectorizer] add test for PR13837; NFC 2018-01-23 22:04:17 +00:00
NVPTX [NVPTX] Turn on Loop/SLP vectorization 2018-04-27 13:36:05 +00:00
PowerPC [SLP] Update tests checks, NFC. 2018-01-05 14:40:04 +00:00
SystemZ [SLPVectorizer] Add tests related to PR30787, NFCI. 2018-03-29 18:57:03 +00:00
X86 [SLPVectorizer] Support alternate opcodes in tryToVectorizeList 2018-06-22 16:37:34 +00:00
XCore
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int_sideeffect.ll Add an @llvm.sideeffect intrinsic 2017-11-08 21:59:51 +00:00