forked from OSchip/llvm-project
89 lines
3.5 KiB
LLVM
89 lines
3.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; LDNT1B
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;
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define <vscale x 16 x i8> @ldnt1b_i8(<vscale x 16 x i1> %pred, <vscale x 16 x i8>* %addr) {
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; CHECK-LABEL: ldnt1b_i8:
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; CHECK: ldnt1b { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %pred,
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<vscale x 16 x i8>* %addr)
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ret <vscale x 16 x i8> %res
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}
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;
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; LDNT1H
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;
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define <vscale x 8 x i16> @ldnt1h_i16(<vscale x 8 x i1> %pred, <vscale x 8 x i16>* %addr) {
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; CHECK-LABEL: ldnt1h_i16:
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; CHECK: ldnt1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %pred,
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<vscale x 8 x i16>* %addr)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 8 x half> @ldnt1h_f16(<vscale x 8 x i1> %pred, <vscale x 8 x half>* %addr) {
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; CHECK-LABEL: ldnt1h_f16:
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; CHECK: ldnt1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %pred,
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<vscale x 8 x half>* %addr)
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ret <vscale x 8 x half> %res
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}
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;
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; LDNT1W
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;
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define <vscale x 4 x i32> @ldnt1w_i32(<vscale x 4 x i1> %pred, <vscale x 4 x i32>* %addr) {
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; CHECK-LABEL: ldnt1w_i32:
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; CHECK: ldnt1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %pred,
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<vscale x 4 x i32>* %addr)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x float> @ldnt1w_f32(<vscale x 4 x i1> %pred, <vscale x 4 x float>* %addr) {
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; CHECK-LABEL: ldnt1w_f32:
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; CHECK: ldnt1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %pred,
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<vscale x 4 x float>* %addr)
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ret <vscale x 4 x float> %res
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}
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;
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; LDNT1D
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;
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define <vscale x 2 x i64> @ldnt1d_i64(<vscale x 2 x i1> %pred, <vscale x 2 x i64>* %addr) {
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; CHECK-LABEL: ldnt1d_i64:
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; CHECK: ldnt1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %pred,
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<vscale x 2 x i64>* %addr)
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x double> @ldnt1d_f64(<vscale x 2 x i1> %pred, <vscale x 2 x double>* %addr) {
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; CHECK-LABEL: ldnt1d_f64:
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; CHECK: ldnt1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %pred,
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<vscale x 2 x double>* %addr)
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ret <vscale x 2 x double> %res
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>*)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>*)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>*)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>*)
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declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, <vscale x 8 x half>*)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>*)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, <vscale x 2 x double>*)
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