forked from OSchip/llvm-project
97 lines
2.8 KiB
LLVM
97 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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define <vscale x 2 x i64> @and_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: and_d
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; CHECK: and z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = and <vscale x 2 x i64> %a, %b
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 4 x i32> @and_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: and_s
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; CHECK: and z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = and <vscale x 4 x i32> %a, %b
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 8 x i16> @and_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: and_h
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; CHECK: and z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = and <vscale x 8 x i16> %a, %b
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 16 x i8> @and_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: and_b
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; CHECK: and z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = and <vscale x 16 x i8> %a, %b
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 2 x i64> @or_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: or_d
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; CHECK: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = or <vscale x 2 x i64> %a, %b
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 4 x i32> @or_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: or_s
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; CHECK: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = or <vscale x 4 x i32> %a, %b
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 8 x i16> @or_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: or_h
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; CHECK: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = or <vscale x 8 x i16> %a, %b
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 16 x i8> @or_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: or_b
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; CHECK: orr z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = or <vscale x 16 x i8> %a, %b
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ret <vscale x 16 x i8> %res
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}
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define <vscale x 2 x i64> @xor_d(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
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; CHECK-LABEL: xor_d
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; CHECK: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = xor <vscale x 2 x i64> %a, %b
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 4 x i32> @xor_s(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
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; CHECK-LABEL: xor_s
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; CHECK: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = xor <vscale x 4 x i32> %a, %b
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 8 x i16> @xor_h(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: xor_h
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; CHECK: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = xor <vscale x 8 x i16> %a, %b
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 16 x i8> @xor_b(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: xor_b
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; CHECK: eor z0.d, z0.d, z1.d
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; CHECK-NEXT: ret
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%res = xor <vscale x 16 x i8> %a, %b
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ret <vscale x 16 x i8> %res
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}
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