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llvm-project/llvm/test/MC/Mips/mips4
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Matheus Almeida 483d7e9349 [mips] Use TwoOperandAliasConstraint for shift instructions. 
This enables TableGen to generate an additional two operand
matcher for our shift_rotate_imm and shift_rotate_reg class of instructions.

The tests were also updated so that they include now encoding information
for all affected instructions.

llvm-svn: 206398
 		2014-04-16 16:28:59 +00:00
..
invalid-mips64-xfail.s [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's 2014-04-03 14:14:22 +00:00
invalid-mips64.s [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's 2014-04-03 14:14:22 +00:00
invalid-mips64r2-xfail.s [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's 2014-04-03 14:14:22 +00:00
invalid-mips64r2.s [mips] Add negative tests confirm that supported ISA's don't allow instructions added in later ISA's 2014-04-03 14:14:22 +00:00
valid-xfail.s [mips] Switch the MIPS-III and MIPS-IV assembler tests to use -mcpu=mips4. 2014-04-10 13:16:49 +00:00
valid.s [mips] Use TwoOperandAliasConstraint for shift instructions. 2014-04-16 16:28:59 +00:00