forked from OSchip/llvm-project
7e52367398
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to correct situations where SelectionDAG and GlobalISel disagree on representation. For example, it would rewrite: (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16> to: (sext:i32 (load:i16 $ptr)<<unindexedload>>) I'd have preferred to replace the fragments and have the expansion happen naturally as part of PatFrag expansion but the type inferencing system can't cope with loads of types narrower than those mentioned in register classes. This is because the SDTCisInt's on the sext constrain both the result and operand to the 'legal' integer types (where legal is defined as 'a register class can contain the type') which immediately rules the narrower types out. Several targets (those with only one legal integer type) would then go on to crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types for the result of the extend. Also, improve isObviouslySafeToFold() slightly to automatically return true for neighbouring instructions. There can't be any re-ordering problems if re-ordering isn't happenning. We'll need to improve it further to handle sign/zero-extending loads when the extend and load aren't immediate neighbours though. llvm-svn: 317971 |
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| .. | ||
| CMakeLists.txt | ||
| CallLowering.cpp | ||
| GlobalISel.cpp | ||
| IRTranslator.cpp | ||
| InstructionSelect.cpp | ||
| InstructionSelector.cpp | ||
| LLVMBuild.txt | ||
| Legalizer.cpp | ||
| LegalizerHelper.cpp | ||
| LegalizerInfo.cpp | ||
| Localizer.cpp | ||
| MachineIRBuilder.cpp | ||
| RegBankSelect.cpp | ||
| RegisterBank.cpp | ||
| RegisterBankInfo.cpp | ||
| Utils.cpp | ||