Sanjay Patel 1319446195 [SLPVectorizer] Try different vectorization factors for store chains ... ...and set max vector register size based on target This patch is based on discussion on the llvmdev mailing list: http://lists.cs.uiuc.edu/pipermail/llvmdev/2015-July/087405.html and also solves: https://llvm.org/bugs/show_bug.cgi?id=17170 Several FIXME/TODO items are noted in comments as potential improvements. Differential Revision: http://reviews.llvm.org/D10950 llvm-svn: 241760		2015-07-08 23:40:55 +00:00
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AArch64	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
AMDGPU	[SLPVectorizer] Try different vectorization factors for store chains	2015-07-08 23:40:55 +00:00
ARM	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00
X86	[SLPVectorizer] Try different vectorization factors for store chains	2015-07-08 23:40:55 +00:00
XCore	[opaque pointer type] Add textual IR support for explicit type parameter to load instruction	2015-02-27 21:17:42 +00:00