Tim Northover 62ae568bbb GlobalISel: implement low-level type with just size & vector lanes. ... This should be all the low-level instruction selection needs to determine how to implement an operation, with the remaining context taken from the opcode (e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math). llvm-svn: 276158		2016-07-20 19:09:30 +00:00
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AArch64	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
AMDGPU	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
ARM	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
Generic	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
Hexagon	[MIR] Print on the given output instead of stderr.	2016-07-13 20:36:03 +00:00
Lanai	[MIR] Print on the given output instead of stderr.	2016-07-13 20:36:03 +00:00
Mips	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
NVPTX	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
PowerPC	llc: Add support for -run-pass none	2016-07-16 02:24:59 +00:00
X86	GlobalISel: implement low-level type with just size & vector lanes.	2016-07-20 19:09:30 +00:00