| .. |
|
AArch64
|
[MachineOutliner] Outline calls
|
2017-12-09 00:43:49 +00:00 |
|
AMDGPU
|
AMDGPU/GCN: Bring processors in sync with AMDGPUUsage
|
2017-12-08 20:52:28 +00:00 |
|
ARC
|
…
|
|
|
ARM
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
|
AVR
|
[AVR] Fix two CodeGen tests
|
2017-12-09 07:51:43 +00:00 |
|
BPF
|
[CodeGen] Print register names in lowercase in both MIR and debug output
|
2017-11-28 17:15:09 +00:00 |
|
Generic
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
Hexagon
|
[Hexagon] Generate HVX code for basic arithmetic operations
|
2017-12-07 17:37:28 +00:00 |
|
Inputs
|
…
|
|
|
Lanai
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
|
MIR
|
Skip DBG instr in OptimizePHIs when looking for dead PHI cycles
|
2017-12-07 07:01:21 +00:00 |
|
MSP430
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
Mips
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
NVPTX
|
[NVPTX,CUDA] Added llvm.nvvm.fns intrinsic and matching __nvvm_fns builtin in clang.
|
2017-12-06 17:50:05 +00:00 |
|
Nios2
|
[Nios2] final infrastructure to provide compilation of a return from a function
|
2017-12-07 12:35:02 +00:00 |
|
PowerPC
|
Temporarily revert "[PowerPC] Allow tail calls of fastcc functions from C CallingConv functions."
|
2017-12-07 22:26:19 +00:00 |
|
RISCV
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
SPARC
|
[CodeGen] Unify MBB reference format in both MIR and debug output
|
2017-12-04 17:18:51 +00:00 |
|
SystemZ
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
|
Thumb
|
[CodeGen] Always use `printReg` to print registers in both MIR and debug
|
2017-11-30 16:12:24 +00:00 |
|
Thumb2
|
[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.
|
2017-12-07 10:40:31 +00:00 |
|
WebAssembly
|
[WebAssembly] Reapply r319186: "Support bitcasted function addresses with varargs."
|
2017-12-08 21:27:00 +00:00 |
|
WinEH
|
…
|
|
|
X86
|
[X86] Improve lowering of vXi1 insert_subvectors to better utilize (insert_subvector zero, vec, 0) for zeroing upper bits.
|
2017-12-09 22:44:42 +00:00 |
|
XCore
|
…
|
|
5ac75d5628