forked from OSchip/llvm-project
232 lines
8.9 KiB
TableGen
232 lines
8.9 KiB
TableGen
//==- SystemZInstrDFP.td - Floating-point SystemZ instructions -*- tblgen-*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The instructions in this file implement SystemZ decimal floating-point
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// arithmetic. These instructions are inot currently used for code generation,
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// are provided for use with the assembler and disassembler only. If LLVM
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// ever supports decimal floating-point types (_Decimal64 etc.), they can
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// also be used for code generation for those types.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Move instructions
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//===----------------------------------------------------------------------===//
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// Load and test.
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let Defs = [CC] in {
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def LTDTR : UnaryRRE<"ltdtr", 0xB3D6, null_frag, FP64, FP64>;
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def LTXTR : UnaryRRE<"ltxtr", 0xB3DE, null_frag, FP128, FP128>;
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}
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//===----------------------------------------------------------------------===//
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// Conversion instructions
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//===----------------------------------------------------------------------===//
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// Convert floating-point values to narrower representations. The destination
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// of LDXTR is a 128-bit value, but only the first register of the pair is used.
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def LEDTR : TernaryRRFe<"ledtr", 0xB3D5, FP32, FP64>;
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def LDXTR : TernaryRRFe<"ldxtr", 0xB3DD, FP128, FP128>;
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// Extend floating-point values to wider representations.
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def LDETR : BinaryRRFd<"ldetr", 0xB3D4, FP64, FP32>;
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def LXDTR : BinaryRRFd<"lxdtr", 0xB3DC, FP128, FP64>;
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// Convert a signed integer value to a floating-point one.
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def CDGTR : UnaryRRE<"cdgtr", 0xB3F1, null_frag, FP64, GR64>;
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def CXGTR : UnaryRRE<"cxgtr", 0xB3F9, null_frag, FP128, GR64>;
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let Predicates = [FeatureFPExtension] in {
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def CDGTRA : TernaryRRFe<"cdgtra", 0xB3F1, FP64, GR64>;
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def CXGTRA : TernaryRRFe<"cxgtra", 0xB3F9, FP128, GR64>;
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def CDFTR : TernaryRRFe<"cdftr", 0xB951, FP64, GR32>;
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def CXFTR : TernaryRRFe<"cxftr", 0xB959, FP128, GR32>;
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}
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// Convert an unsigned integer value to a floating-point one.
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let Predicates = [FeatureFPExtension] in {
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def CDLGTR : TernaryRRFe<"cdlgtr", 0xB952, FP64, GR64>;
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def CXLGTR : TernaryRRFe<"cxlgtr", 0xB95A, FP128, GR64>;
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def CDLFTR : TernaryRRFe<"cdlftr", 0xB953, FP64, GR32>;
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def CXLFTR : TernaryRRFe<"cxlftr", 0xB95B, FP128, GR32>;
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}
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// Convert a floating-point value to a signed integer value.
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let Defs = [CC] in {
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def CGDTR : BinaryRRFe<"cgdtr", 0xB3E1, GR64, FP64>;
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def CGXTR : BinaryRRFe<"cgxtr", 0xB3E9, GR64, FP128>;
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let Predicates = [FeatureFPExtension] in {
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def CGDTRA : TernaryRRFe<"cgdtra", 0xB3E1, GR64, FP64>;
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def CGXTRA : TernaryRRFe<"cgxtra", 0xB3E9, GR64, FP128>;
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def CFDTR : TernaryRRFe<"cfdtr", 0xB941, GR32, FP64>;
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def CFXTR : TernaryRRFe<"cfxtr", 0xB949, GR32, FP128>;
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}
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}
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// Convert a floating-point value to an unsigned integer value.
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let Defs = [CC] in {
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let Predicates = [FeatureFPExtension] in {
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def CLGDTR : TernaryRRFe<"clgdtr", 0xB942, GR64, FP64>;
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def CLGXTR : TernaryRRFe<"clgxtr", 0xB94A, GR64, FP128>;
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def CLFDTR : TernaryRRFe<"clfdtr", 0xB943, GR32, FP64>;
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def CLFXTR : TernaryRRFe<"clfxtr", 0xB94B, GR32, FP128>;
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}
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}
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// Convert a packed value to a floating-point one.
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def CDSTR : UnaryRRE<"cdstr", 0xB3F3, null_frag, FP64, GR64>;
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def CXSTR : UnaryRRE<"cxstr", 0xB3FB, null_frag, FP128, GR128>;
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def CDUTR : UnaryRRE<"cdutr", 0xB3F2, null_frag, FP64, GR64>;
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def CXUTR : UnaryRRE<"cxutr", 0xB3FA, null_frag, FP128, GR128>;
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// Convert a floating-point value to a packed value.
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def CSDTR : BinaryRRFd<"csdtr", 0xB3E3, GR64, FP64>;
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def CSXTR : BinaryRRFd<"csxtr", 0xB3EB, GR128, FP128>;
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def CUDTR : UnaryRRE<"cudtr", 0xB3E2, null_frag, GR64, FP64>;
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def CUXTR : UnaryRRE<"cuxtr", 0xB3EA, null_frag, GR128, FP128>;
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// Convert from/to memory values in the zoned format.
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let Predicates = [FeatureDFPZonedConversion] in {
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def CDZT : BinaryRSL<"cdzt", 0xEDAA, FP64>;
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def CXZT : BinaryRSL<"cxzt", 0xEDAB, FP128>;
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def CZDT : StoreBinaryRSL<"czdt", 0xEDA8, FP64>;
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def CZXT : StoreBinaryRSL<"czxt", 0xEDA9, FP128>;
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}
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// Convert from/to memory values in the packed format.
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let Predicates = [FeatureDFPPackedConversion] in {
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def CDPT : BinaryRSL<"cdpt", 0xEDAE, FP64>;
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def CXPT : BinaryRSL<"cxpt", 0xEDAF, FP128>;
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def CPDT : StoreBinaryRSL<"cpdt", 0xEDAC, FP64>;
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def CPXT : StoreBinaryRSL<"cpxt", 0xEDAD, FP128>;
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}
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// Perform floating-point operation.
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let Defs = [CC, R1L, F0Q], Uses = [R0L, F4Q] in
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def PFPO : SideEffectInherentE<"pfpo", 0x010A>;
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//===----------------------------------------------------------------------===//
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// Unary arithmetic
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//===----------------------------------------------------------------------===//
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// Round to an integer, with the second operand (M3) specifying the rounding
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// mode. M4 can be set to 4 to suppress detection of inexact conditions.
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def FIDTR : TernaryRRFe<"fidtr", 0xB3D7, FP64, FP64>;
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def FIXTR : TernaryRRFe<"fixtr", 0xB3DF, FP128, FP128>;
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// Extract biased exponent.
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def EEDTR : UnaryRRE<"eedtr", 0xB3E5, null_frag, FP64, FP64>;
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def EEXTR : UnaryRRE<"eextr", 0xB3ED, null_frag, FP128, FP128>;
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// Extract significance.
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def ESDTR : UnaryRRE<"esdtr", 0xB3E7, null_frag, FP64, FP64>;
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def ESXTR : UnaryRRE<"esxtr", 0xB3EF, null_frag, FP128, FP128>;
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//===----------------------------------------------------------------------===//
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// Binary arithmetic
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//===----------------------------------------------------------------------===//
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// Addition.
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let Defs = [CC] in {
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let isCommutable = 1 in {
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def ADTR : BinaryRRFa<"adtr", 0xB3D2, null_frag, FP64, FP64, FP64>;
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def AXTR : BinaryRRFa<"axtr", 0xB3DA, null_frag, FP128, FP128, FP128>;
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}
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let Predicates = [FeatureFPExtension] in {
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def ADTRA : TernaryRRFa<"adtra", 0xB3D2, FP64, FP64, FP64>;
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def AXTRA : TernaryRRFa<"axtra", 0xB3DA, FP128, FP128, FP128>;
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}
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}
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// Subtraction.
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let Defs = [CC] in {
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def SDTR : BinaryRRFa<"sdtr", 0xB3D3, null_frag, FP64, FP64, FP64>;
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def SXTR : BinaryRRFa<"sxtr", 0xB3DB, null_frag, FP128, FP128, FP128>;
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let Predicates = [FeatureFPExtension] in {
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def SDTRA : TernaryRRFa<"sdtra", 0xB3D3, FP64, FP64, FP64>;
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def SXTRA : TernaryRRFa<"sxtra", 0xB3DB, FP128, FP128, FP128>;
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}
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}
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// Multiplication.
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let isCommutable = 1 in {
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def MDTR : BinaryRRFa<"mdtr", 0xB3D0, null_frag, FP64, FP64, FP64>;
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def MXTR : BinaryRRFa<"mxtr", 0xB3D8, null_frag, FP128, FP128, FP128>;
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}
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let Predicates = [FeatureFPExtension] in {
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def MDTRA : TernaryRRFa<"mdtra", 0xB3D0, FP64, FP64, FP64>;
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def MXTRA : TernaryRRFa<"mxtra", 0xB3D8, FP128, FP128, FP128>;
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}
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// Division.
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def DDTR : BinaryRRFa<"ddtr", 0xB3D1, null_frag, FP64, FP64, FP64>;
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def DXTR : BinaryRRFa<"dxtr", 0xB3D9, null_frag, FP128, FP128, FP128>;
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let Predicates = [FeatureFPExtension] in {
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def DDTRA : TernaryRRFa<"ddtra", 0xB3D1, FP64, FP64, FP64>;
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def DXTRA : TernaryRRFa<"dxtra", 0xB3D9, FP128, FP128, FP128>;
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}
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// Quantize.
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def QADTR : TernaryRRFb<"qadtr", 0xB3F5, FP64, FP64, FP64>;
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def QAXTR : TernaryRRFb<"qaxtr", 0xB3FD, FP128, FP128, FP128>;
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// Reround.
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def RRDTR : TernaryRRFb<"rrdtr", 0xB3F7, FP64, FP64, FP64>;
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def RRXTR : TernaryRRFb<"rrxtr", 0xB3FF, FP128, FP128, FP128>;
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// Shift significand left/right.
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def SLDT : BinaryRXF<"sldt", 0xED40, null_frag, FP64, FP64, null_frag, 0>;
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def SLXT : BinaryRXF<"slxt", 0xED48, null_frag, FP128, FP128, null_frag, 0>;
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def SRDT : BinaryRXF<"srdt", 0xED41, null_frag, FP64, FP64, null_frag, 0>;
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def SRXT : BinaryRXF<"srxt", 0xED49, null_frag, FP128, FP128, null_frag, 0>;
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// Insert biased exponent.
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def IEDTR : BinaryRRFb<"iedtr", 0xB3F6, null_frag, FP64, FP64, FP64>;
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def IEXTR : BinaryRRFb<"iextr", 0xB3FE, null_frag, FP128, FP128, FP128>;
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//===----------------------------------------------------------------------===//
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// Comparisons
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//===----------------------------------------------------------------------===//
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// Compare.
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let Defs = [CC] in {
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def CDTR : CompareRRE<"cdtr", 0xB3E4, null_frag, FP64, FP64>;
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def CXTR : CompareRRE<"cxtr", 0xB3EC, null_frag, FP128, FP128>;
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}
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// Compare and signal.
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let Defs = [CC] in {
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def KDTR : CompareRRE<"kdtr", 0xB3E0, null_frag, FP64, FP64>;
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def KXTR : CompareRRE<"kxtr", 0xB3E8, null_frag, FP128, FP128>;
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}
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// Compare biased exponent.
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let Defs = [CC] in {
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def CEDTR : CompareRRE<"cedtr", 0xB3F4, null_frag, FP64, FP64>;
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def CEXTR : CompareRRE<"cextr", 0xB3FC, null_frag, FP128, FP128>;
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}
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// Test Data Class.
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let Defs = [CC] in {
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def TDCET : TestRXE<"tdcet", 0xED50, null_frag, FP32>;
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def TDCDT : TestRXE<"tdcdt", 0xED54, null_frag, FP64>;
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def TDCXT : TestRXE<"tdcxt", 0xED58, null_frag, FP128>;
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}
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// Test Data Group.
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let Defs = [CC] in {
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def TDGET : TestRXE<"tdget", 0xED51, null_frag, FP32>;
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def TDGDT : TestRXE<"tdgdt", 0xED55, null_frag, FP64>;
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def TDGXT : TestRXE<"tdgxt", 0xED59, null_frag, FP128>;
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}
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