forked from OSchip/llvm-project
99 lines
2.4 KiB
TableGen
99 lines
2.4 KiB
TableGen
//===-- MipsMTInstrFormats.td - Mips Instruction Formats ---*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Describe the MIPS MT instructions format
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//
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// opcode - operation code.
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// rt - destination register
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//
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//===----------------------------------------------------------------------===//
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class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
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let DecoderNamespace = "Mips";
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let EncodingPredicates = [HasStdEnc];
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}
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class OPCODE1<bits<1> Val> {
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bits<1> Value = Val;
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}
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def OPCODE_SC_D : OPCODE1<0b0>;
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def OPCODE_SC_E : OPCODE1<0b1>;
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class FIELD5<bits<5> Val> {
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bits<5> Value = Val;
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}
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def FIELD5_1_DMT_EMT : FIELD5<0b00001>;
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def FIELD5_2_DMT_EMT : FIELD5<0b01111>;
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def FIELD5_1_2_DVPE_EVPE : FIELD5<0b00000>;
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def FIELD5_MFTR : FIELD5<0b01000>;
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def FIELD5_MTTR : FIELD5<0b01100>;
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class COP0_MFMC0_MT<FIELD5 Op1, FIELD5 Op2, OPCODE1 sc> : MipsMTInst {
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bits<32> Inst;
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bits<5> rt;
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let Inst{31-26} = 0b010000; // COP0
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let Inst{25-21} = 0b01011; // MFMC0
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let Inst{20-16} = rt;
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let Inst{15-11} = Op1.Value;
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let Inst{10-6} = Op2.Value;
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let Inst{5} = sc.Value;
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let Inst{4-3} = 0b00;
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let Inst{2-0} = 0b001;
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}
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class COP0_MFTTR_MT<FIELD5 Op> : MipsMTInst {
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bits<32> Inst;
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bits<5> rt;
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bits<5> rd;
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bits<1> u;
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bits<1> h;
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bits<3> sel;
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let Inst{31-26} = 0b010000; // COP0
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let Inst{25-21} = Op.Value; // MFMC0
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00000; // rx - currently unsupported.
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let Inst{5} = u;
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let Inst{4} = h;
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let Inst{3} = 0b0;
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let Inst{2-0} = sel;
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}
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class SPECIAL3_MT_FORK : MipsMTInst {
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bits<32> Inst;
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bits<5> rs;
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bits<5> rt;
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bits<5> rd;
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let Inst{31-26} = 0b011111; // SPECIAL3
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00000;
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let Inst{5-0} = 0b001000; // FORK
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}
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class SPECIAL3_MT_YIELD : MipsMTInst {
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bits<32> Inst;
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bits<5> rs;
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bits<5> rd;
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let Inst{31-26} = 0b011111; // SPECIAL3
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let Inst{25-21} = rs;
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let Inst{20-16} = 0b00000;
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let Inst{15-11} = rd;
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let Inst{10-6} = 0b00000;
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let Inst{5-0} = 0b001001; // FORK
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}
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