forked from OSchip/llvm-project
509 lines
16 KiB
TableGen
509 lines
16 KiB
TableGen
//===- ARCInstrFormats.td - ARC Instruction Formats --------*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class Encoding64 {
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field bits<64> Inst;
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field bits<64> SoftFail = 0;
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}
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// Address operands
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def immU6 : Operand<i32>, PatLeaf<(imm), [{
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return isUInt<6>(N->getSExtValue()); }]> {
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}
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def immS12 : Operand<i32>, PatLeaf<(imm), [{
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return isInt<12>(N->getSExtValue()); }]> {
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let DecoderMethod = "DecodeS12Operand";
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}
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def immS9 : Operand<i32>, PatLeaf<(imm), [{
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return isInt<9>(N->getSExtValue()); }]> {
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let DecoderMethod = "DecodeS9Operand";
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}
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def MEMii : Operand<i32> {
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let MIOperandInfo = (ops i32imm, i32imm);
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}
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def MEMrs9 : Operand<iAny> {
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let MIOperandInfo = (ops GPR32:$B, immS9:$S9);
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let PrintMethod = "printMemOperandRI";
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let DecoderMethod = "DecodeMEMrs9";
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}
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def MEMrlimm : Operand<iAny> {
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let MIOperandInfo = (ops GPR32:$B, i32imm:$LImm);
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let PrintMethod = "printMemOperandRI";
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let DecoderMethod = "DecodeMEMrlimm";
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}
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class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
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: Instruction, Encoding64 {
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let Namespace = "ARC";
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dag OutOperandList = outs;
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dag InOperandList = ins;
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let AsmString = asmstr;
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let Pattern = pattern;
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let Size = sz;
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}
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// ARC pseudo instructions format
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class PseudoInstARC<dag outs, dag ins, string asmstr, list<dag> pattern>
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: InstARC<0, outs, ins, asmstr, pattern> {
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let isPseudo = 1;
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}
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//===----------------------------------------------------------------------===//
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// Instruction formats
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//===----------------------------------------------------------------------===//
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// All 32-bit ARC instructions have a 5-bit "major" opcode class designator
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// in bits 27-31.
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//
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// Some general naming conventions:
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// N - Delay Slot bit. ARC v2 branch instructions have an optional delay slot
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// which is encoded with this bit. When set, a delay slot exists.
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// cc - Condition code.
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// SX - Signed X-bit immediate.
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// UX - Unsigned X-bit immediate.
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//
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// [ABC] - 32-bit register operand. These are 6-bit fields. This encodes the
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// standard 32 general purpose registers, and allows use of additional
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// (extension) registers. This also encodes an instruction that uses
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// a 32-bit Long Immediate (LImm), using 0x3e==62 as the field value.
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// This makes 32-bit format instructions with Long Immediates
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// 64-bit instructions, with the Long Immediate in bits 32-63.
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// A - Inst[5-0] = A[5-0], when the format has A. A is always a register.
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// B - Inst[14-12] = B[5-3], Inst[26-24] = B[2-0], when the format has B.
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// B is always a register.
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// C - Inst[11-6] = C[5-0], when the format has C. C can either be a register,
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// or a 6-bit unsigned immediate (immU6), depending on the format.
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// F - Many instructions specify a flag bit. When set, the result of these
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// instructions will set the ZNCV flags of the STATUS32 register
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// (Zero/Negative/Carry/oVerflow).
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// Branch Instructions.
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class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
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list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bit N;
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let Inst{31-27} = major;
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let Inst{16} = b16;
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let Inst{5} = N;
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}
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class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
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list<dag> pattern> :
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F32_BR<major, outs, ins, b16, asmstr, pattern> {
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bits<21> S21; // 2-byte aligned 21-bit byte-offset.
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bits<5> cc;
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let Inst{26-18} = S21{10-2};
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let Inst{15-6} = S21{20-11};
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let Inst{4-0} = cc;
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}
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class F32_BR_UCOND_FAR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
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list<dag> pattern> :
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F32_BR<major, outs, ins, b16, asmstr, pattern> {
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bits<25> S25; // 2-byte aligned 25-bit byte-offset.
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let Inst{26-18} = S25{10-2};
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let Inst{15-6} = S25{20-11};
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let Inst{4} = 0;
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let Inst{3-0} = S25{24-21};
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}
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class F32_BR0_COND<dag outs, dag ins, string asmstr, list<dag> pat> :
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F32_BR_COND<0b00000, outs, ins, 0, asmstr, pat> {
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let Inst{17} = S21{1};
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}
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// Branch targets are 2-byte aligned, so S25[0] is implied 0.
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
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// |S25[10-1] | 1|S25[20-11] |N|0|S25[24-21]|
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class F32_BR0_UCOND_FAR<dag outs, dag ins, string asmstr, list<dag> pat> :
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F32_BR_UCOND_FAR<0b00000, outs, ins, 1, asmstr, pat> {
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let Inst{17} = S25{1};
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}
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// BL targets (functions) are 4-byte aligned, so S25[1-0] = 0b00
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0 |
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// |S25[10-2] | 1| 0|S25[20-11] |N|0|S25[24-21]|
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class F32_BR1_BL_UCOND_FAR<dag outs, dag ins, string asmstr, list<dag> pat> :
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F32_BR_UCOND_FAR<0b00001, outs, ins, 0, asmstr, pat> {
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let Inst{17} = 1;
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}
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// BLcc targets have 21 bit range, and are 4-byte aligned.
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |S25[10-2] | 0| 0|S25[20-11] |N|0|cc |
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class F32_BR1_BL_COND<dag outs, dag ins, string asmstr, list<dag> pat> :
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F32_BR_COND<0b00001, outs, ins, 0, asmstr, pat> {
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let Inst{17} = 0;
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}
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// BRcc targets have limited 9-bit range. These are for compare and branch
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// in single instruction. Their targets are 2-byte aligned. They also use
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// a different (3-bit) set of condition codes.
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// |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] |S9[7-1] | 1|S9[8]|B[5-3] |C |N|u|0|cc |
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class F32_BR1_BCC<dag outs, dag ins, string asmstr, bit IsU6,
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list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bits<3> cc;
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bits<6> B;
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bits<6> C;
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bit N;
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bits<9> S9; // 2-byte aligned 9-bit byte-offset.
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let Inst{31-27} = 0b00001;
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let Inst{26-24} = B{2-0};
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let Inst{23-17} = S9{7-1};
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let Inst{16} = 1;
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let Inst{15} = S9{8};
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let Inst{14-12} = B{5-3};
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let Inst{11-6} = C;
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let Inst{5} = N;
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let Inst{4} = IsU6;
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let Inst{3} = 0;
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let Inst{2-0} = cc;
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}
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// General operations instructions.
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// Single Operand Instructions. Inst[5-0] specifies the specific operation
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// for this format.
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] | 0| 0| 1| 0| 1| 1| 1| 1| F|B[5-3] |C |subop |
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class F32_SOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bits<6> C;
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bits<6> B;
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let Inst{31-27} = major;
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let Inst{26-24} = B{2-0};
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let Inst{23-22} = 0b00;
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let Inst{21-16} = 0b101111;
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let Inst{15} = F;
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let Inst{14-12} = B{5-3};
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let Inst{11-6} = C;
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let Inst{5-0} = subop;
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}
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// Dual Operand Instructions. Inst[21-16] specifies the specific operation
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// for this format.
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// 3-register Dual Operand instruction.
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] | 0| 0| subop| F|B[5-3] |C |A |
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class F32_DOP_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bits<6> C;
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bits<6> B;
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bits<6> A;
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let Inst{31-27} = major;
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let Inst{26-24} = B{2-0};
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let Inst{23-22} = 0b00;
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let Inst{21-16} = subop;
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let Inst{15} = F;
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let Inst{14-12} = B{5-3};
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let Inst{11-6} = C;
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let Inst{5-0} = A;
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}
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// Conditional Dual Operand instruction. This instruction uses B as the
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// first 2 operands (i.e, add.cc B, B, C).
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] | 1| 1| subop| F|B[5-3] |C |A |
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class F32_DOP_CC_RR<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bits<5> cc;
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bits<6> C;
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bits<6> B;
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let Inst{31-27} = major;
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let Inst{26-24} = B{2-0};
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let Inst{23-22} = 0b11;
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let Inst{21-16} = subop;
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let Inst{15} = F;
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let Inst{14-12} = B{5-3};
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let Inst{11-6} = C;
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let Inst{5} = 0;
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let Inst{4-0} = cc;
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}
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// 2-register, unsigned 6-bit immediate Dual Operand instruction.
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] | 0| 1| subop| F|B[5-3] |U6 |A |
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class F32_DOP_RU6<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bits<6> U6;
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bits<6> B;
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bits<6> A;
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let Inst{31-27} = major;
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let Inst{26-24} = B{2-0};
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let Inst{23-22} = 0b01;
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let Inst{21-16} = subop;
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let Inst{15} = F;
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let Inst{14-12} = B{5-3};
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let Inst{11-6} = U6;
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let Inst{5-0} = A;
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}
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// 2-register, signed 12-bit immediate Dual Operand instruction.
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// This instruction uses B as the first 2 operands (i.e., add B, B, -128).
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] | 1| 0| subop| F|B[5-3] |S12[5-0] |S12[11-6] |
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class F32_DOP_RS12<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bits<6> B;
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bits<12> S12;
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let Inst{31-27} = major;
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let Inst{26-24} = B{2-0};
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let Inst{23-22} = 0b10;
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let Inst{21-16} = subop;
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let Inst{15} = F;
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let Inst{14-12} = B{5-3};
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let Inst{11-6} = S12{5-0};
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let Inst{5-0} = S12{11-6};
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}
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// 2-register, 32-bit immediate (LImm) Dual Operand instruction.
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// This instruction has the 32-bit immediate in bits 32-63, and
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// 62 in the C register operand slot, but is otherwise F32_DOP_RR.
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class F32_DOP_RLIMM<bits<5> major, bits<6> subop, bit F, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<8, outs, ins, asmstr, pattern> {
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bits<6> B;
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bits<6> A;
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bits<32> LImm;
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let Inst{63-32} = LImm;
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let Inst{31-27} = major;
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let Inst{26-24} = B{2-0};
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let Inst{23-22} = 0b00;
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let Inst{21-16} = subop;
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let Inst{15} = F;
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let Inst{14-12} = B{5-3};
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let Inst{11-6} = 0b111110;
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let Inst{5-0} = A;
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}
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// Load and store instructions.
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// In addition to the previous naming conventions, load and store instructions
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// have:
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// di - Uncached bit. When set, loads/stores bypass the cache and access
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// memory directly.
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// aa - Incrementing mode. Loads and stores can write-back address pre- or
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// post- memory operation.
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// zz - Memory size (can be 8/16/32 bit load/store).
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// x - Sign-extending. When set, short loads can be sign-extended to 32-bits.
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// Loads and Stores support different memory addressing modes:
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// Base Register + Signed 9-bit Immediate: Both Load/Store.
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// LImm: Both Load/Store (Load/Store from a fixed 32-bit address).
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// Register + Register: Load Only.
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// Register + LImm: Load Only.
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// Register + S9 Load. (B + S9)
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// |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] |S9[7-0] |S9[8]|B[5-3] |di|aa |zz |x|A |
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class F32_LD_RS9<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<4, outs, ins, asmstr, pattern> {
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bits<6> B;
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bits<6> A;
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bits<9> S9;
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let Inst{31-27} = 0b00010;
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let Inst{26-24} = B{2-0};
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let Inst{23-16} = S9{7-0};
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let Inst{15} = S9{8};
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let Inst{14-12} = B{5-3};
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let Inst{11} = di;
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let Inst{10-9} = aa;
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let Inst{8-7} = zz;
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let Inst{6} = x;
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let Inst{5-0} = A;
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}
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class F32_LD_ADDR<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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F32_LD_RS9<x, aa, di, zz, outs, ins, asmstr, pattern> {
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bits<15> addr;
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let B = addr{14-9};
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let S9 = addr{8-0};
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}
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// LImm Load. The 32-bit immediate address is in Inst[63-32].
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// | 1| 1| 0| 0 | 1| 1| 1|di| 0|0|zz |x|A |
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class F32_LD_LIMM<bit x, bit di, bits<2> zz, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<8, outs, ins, asmstr, pattern> {
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bits<6> LImmReg = 0b111110;
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bits<6> A;
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bits<32> LImm;
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let Inst{63-32} = LImm;
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let Inst{31-27} = 0b00010;
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let Inst{26-24} = LImmReg{2-0};
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let Inst{23-15} = 0;
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let Inst{14-12} = LImmReg{5-3};
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let Inst{11} = di;
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let Inst{10-9} = 0;
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let Inst{8-7} = zz;
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let Inst{6} = x;
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let Inst{5-0} = A;
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let DecoderMethod = "DecodeLdLImmInstruction";
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}
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// Register + LImm load. The 32-bit immediate address is in Inst[63-32].
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// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5|4|3|2|1|0|
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// |B[2-0] |aa | 1| 1| 0|zz | x|di|B[5-3] | 1| 1|1|1|1|0|A |
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class F32_LD_RLIMM<bit x, bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
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string asmstr, list<dag> pattern> :
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InstARC<8, outs, ins, asmstr, pattern> {
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bits<6> LImmReg = 0b111110;
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bits<32> LImm;
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bits<6> B;
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bits<6> A;
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bits<38> addr;
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let B = addr{37-32};
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let LImm = addr{31-0};
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let Inst{63-32} = LImm;
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let Inst{31-27} = 0b00100;
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let Inst{26-24} = B{2-0};
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let Inst{23-22} = aa;
|
|
let Inst{21-19} = 0b110;
|
|
let Inst{18-17} = zz;
|
|
let Inst{16} = x;
|
|
let Inst{15} = di;
|
|
let Inst{14-12} = B{5-3};
|
|
let Inst{11-6} = LImmReg;
|
|
let Inst{5-0} = A;
|
|
let DecoderMethod = "DecodeLdRLImmInstruction";
|
|
}
|
|
|
|
// Register + S9 Store. (B + S9)
|
|
// |26|25|24|23|22|21|20|19|18|17|16|15 |14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
|
|
// |B[2-0] |S9[7-0] |S9[8]|B[5-3] |C |di|aa |zz |0|
|
|
class F32_ST_RS9<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
|
|
string asmstr, list<dag> pattern> :
|
|
InstARC<4, outs, ins, asmstr, pattern> {
|
|
bits<6> B;
|
|
bits<6> C;
|
|
bits<9> S9;
|
|
|
|
let Inst{31-27} = 0b00011;
|
|
let Inst{26-24} = B{2-0};
|
|
let Inst{23-16} = S9{7-0};
|
|
let Inst{15} = S9{8};
|
|
let Inst{14-12} = B{5-3};
|
|
let Inst{11-6} = C;
|
|
let Inst{5} = di;
|
|
let Inst{4-3} = aa;
|
|
let Inst{2-1} = zz;
|
|
let Inst{0} = 0;
|
|
}
|
|
|
|
class F32_ST_ADDR<bits<2> aa, bit di, bits<2> zz, dag outs, dag ins,
|
|
string asmstr, list<dag> pattern> :
|
|
F32_ST_RS9<aa, di, zz, outs, ins, asmstr, pattern> {
|
|
bits<15> addr;
|
|
|
|
let B = addr{14-9};
|
|
let S9 = addr{8-0};
|
|
}
|
|
|
|
// LImm Store.
|
|
// |26|25|24|23|22|21|20|19|18|17|16|15|14|13|12|11|10|9|8|7|6|5 |4|3|2|1|0|
|
|
// | 1| 1| 0| 0 | 1| 1| 1|C |di|0|0|zz |0|
|
|
class F32_ST_LIMM<bit di, bits<2> zz, dag outs, dag ins,
|
|
string asmstr, list<dag> pattern> :
|
|
InstARC<8, outs, ins, asmstr, pattern> {
|
|
bits<6> LImmReg = 0b111110;
|
|
bits<6> C;
|
|
bits<32> LImm;
|
|
|
|
let Inst{63-32} = LImm;
|
|
let Inst{31-27} = 0b00011;
|
|
let Inst{26-24} = LImmReg{2-0};
|
|
let Inst{23-15} = 0;
|
|
let Inst{14-12} = LImmReg{5-3};
|
|
let Inst{11-6} = C;
|
|
let Inst{5} = di;
|
|
let Inst{4-3} = 0;
|
|
let Inst{2-1} = zz;
|
|
let Inst{0} = 0;
|
|
let DecoderMethod = "DecodeStLImmInstruction";
|
|
}
|
|
|
|
// Special types for different instruction operands.
|
|
def cmovpred : Operand<i32>, PredicateOp,
|
|
ComplexPattern<i32, 2, "SelectCMOVPred"> {
|
|
let MIOperandInfo = (ops i32imm, i32imm);
|
|
let PrintMethod = "printPredicateOperand";
|
|
}
|
|
|
|
def ccond : Operand<i32> {
|
|
let MIOperandInfo = (ops i32imm);
|
|
let PrintMethod = "printPredicateOperand";
|
|
}
|
|
|
|
def brccond : Operand<i32> {
|
|
let MIOperandInfo = (ops i32imm);
|
|
let PrintMethod = "printBRCCPredicateOperand";
|
|
}
|
|
|
|
// Branch targets of different offset sizes.
|
|
def btarget : Operand<OtherVT> {
|
|
let OperandType = "OPERAND_PCREL";
|
|
}
|
|
|
|
def btargetS9 : Operand<OtherVT> {
|
|
let OperandType = "OPERAND_PCREL";
|
|
let DecoderMethod = "DecodeBranchTargetS9";
|
|
}
|
|
|
|
def btargetS21 : Operand<OtherVT> {
|
|
let OperandType = "OPERAND_PCREL";
|
|
let DecoderMethod = "DecodeBranchTargetS21";
|
|
}
|
|
|
|
def btargetS25 : Operand<OtherVT> {
|
|
let OperandType = "OPERAND_PCREL";
|
|
let DecoderMethod = "DecodeBranchTargetS25";
|
|
}
|
|
|
|
def calltargetS25: Operand<i32> {
|
|
let OperandType = "OPERAND_PCREL";
|
|
let DecoderMethod = "DecodeBranchTargetS25";
|
|
}
|
|
|