Simon Pilgrim bbb0933e3d [DAG] visitRotate - modulo non-uniform constant rotation amounts		2020-02-26 15:43:12 +00:00
..
AArch64	[AArch64][SVE] Add SVE2 intrinsics for bit permutation & table lookup	2020-02-26 11:22:23 +00:00
AMDGPU	AMDGPU: Fix some more incorrect check lines	2020-02-26 14:37:22 +00:00
ARC	…
ARM	Don't generate libcalls for wide shift on Windows ARM (PR42711)	2020-02-25 11:54:07 +01:00
AVR	…
BPF	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
Generic	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
Hexagon	[Hexagon] Lower vector predicate store	2020-02-24 15:43:04 -06:00
Inputs	…
Lanai	Revert "Revert "Reland "[Support] make report_fatal_error `abort` instead of `exit`"""	2020-02-13 10:16:06 -08:00
MIR	[MIR][ARM] MachineOperand comments	2020-02-24 14:19:21 +00:00
MSP430	…
Mips	[MIPS GlobalISel] Legalize non-power-of-2 and unaligned load and store	2020-02-19 12:02:27 +01:00
NVPTX	[NVPTX, LSV] Move the LSV optimization pass to later when the graph is cleaner	2020-02-13 12:15:38 -08:00
PowerPC	[AIX] Remove whitelist checking for ExternalSymbolSDNodes	2020-02-26 10:09:25 -05:00
RISCV	[RISCV] Implement mayBeEmittedAsTailCall for tail call optimization	2020-02-18 23:56:42 +08:00
SPARC	Emit register names in cfi assembly directives	2020-02-25 14:00:01 -05:00
SystemZ	[LegalizeTypes] Scalarize non-byte sized loads in WidenRecRes_Load and SplitVecResLoad	2020-02-24 15:14:33 -08:00
Thumb	[MIR][ARM] MachineOperand comments	2020-02-24 14:19:21 +00:00
Thumb2	[ARM,MVE] Add predicated intrinsics for many unary functions.	2020-02-26 15:12:07 +00:00
VE	[VE] TLS codegen	2020-02-18 16:09:12 +01:00
WebAssembly	[WebAssembly] Simplify extract_vector lowering	2020-02-25 13:54:48 -08:00
WinCFGuard	…
WinEH	…
X86	[DAG] visitRotate - modulo non-uniform constant rotation amounts	2020-02-26 15:43:12 +00:00
XCore	[XCore] Add instruction pattern for bitrev	2020-02-21 09:28:49 +08:00