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llvm-project/llvm/test/CodeGen/MIR/AMDGPU
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Matt Arsenault 66d60e06cb AMDGPU: Serialize MFI spill fields 
These should probably be inferred from the function on parse, but the
target specific infrastructure currently does not give you a way to do
this. SILowerSGPRSpills early exits without this reporting spills,
which makes it difficult to write a MIR test for.
 		2020-07-28 20:01:57 -04:00
..
expected-target-index-name.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
intrinsics.mir
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invalid-target-index-operand.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
lit.local.cfg
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llc-target-cpu-attr-from-cmdline-ir.mir llc: Change behavior of -mcpu with existing attribute 2020-01-07 10:10:25 -05:00
llc-target-cpu-attr-from-cmdline.mir llc/MIR: Fix setFunctionAttributes for MIR functions 2020-01-06 17:21:51 -05:00
load-store-opt-dlc.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00
machine-function-info-no-ir.mir AMDGPU: Serialize MFI spill fields 2020-07-28 20:01:57 -04:00
machine-function-info-register-parse-error1.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
machine-function-info-register-parse-error2.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
machine-function-info.ll AMDGPU: Serialize MFI spill fields 2020-07-28 20:01:57 -04:00
mfi-frame-offset-reg-class.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-parse-error-frame-offset-reg.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-parse-error-scratch-rsrc-reg.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-parse-error-stack-ptr-offset-reg.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-scratch-rsrc-reg-reg-class.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mfi-stack-ptr-offset-reg-class.mir [AMDGPU] Avoid hard-coded line numbers in error message checks 2020-04-23 21:06:09 +01:00
mir-canon-multi.mir [MIRNamer]: Make the check lines in the test robust with regex. 2019-11-16 22:58:45 -08:00
mircanon-memoperands.mir [llvm][MIRVRegNamerUtils] Adding hashing on memoperands. 2019-12-11 22:11:49 -05:00
parse-order-reserved-regs.mir [AMDGPU] Add Scratch Wave Offset to Scratch Buffer Descriptor in entry functions 2020-03-19 15:35:16 -04:00
stack-id.mir
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syncscopes.mir
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target-flags.mir
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target-index-operands.mir [AMDGPU] Extend buffer intrinsics with swizzling 2019-10-02 17:22:36 +00:00