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llvm-project/llvm/test/CodeGen/MIR
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Matt Arsenault 66d60e06cb AMDGPU: Serialize MFI spill fields 
These should probably be inferred from the function on parse, but the
target specific infrastructure currently does not give you a way to do
this. SILowerSGPRSpills early exits without this reporting spills,
which makes it difficult to write a MIR test for.
 		2020-07-28 20:01:57 -04:00
..
AArch64 [MIR] Fix CFI_INSTRUCTION escape printing 2020-06-24 18:15:28 -04:00
AMDGPU AMDGPU: Serialize MFI spill fields 2020-07-28 20:01:57 -04:00
ARM [ARM] Track epilogue instructions with FrameDestroy flag (NFC) 2020-03-18 13:32:59 +00:00
Generic [MIR] Fix CFI_INSTRUCTION escape printing 2020-06-24 18:15:28 -04:00
Hexagon Reland D73534: [DebugInfo] Enable the debug entry values feature by default 2020-03-19 13:57:30 +01:00
Mips [MIParser] Set RegClassOrRegBank during instruction parsing 2019-10-22 14:25:37 +00:00
NVPTX
…
PowerPC [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPC 2019-09-13 14:18:36 +00:00
WebAssembly [WebAssembly] Fix tests missed in rL374235 2019-10-09 23:06:38 +00:00
X86 [llvm-readobj] Update tests because of changes in llvm-readobj behavior 2020-07-20 10:39:04 +01:00
README
…

README 

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.