forked from OSchip/llvm-project
174 lines
5.8 KiB
LLVM
174 lines
5.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instcombine -S | FileCheck %s
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; If we have a shift by sign-extended value, we can replace sign-extension
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; with zero-extension.
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define i32 @t0_shl(i32 %x, i8 %shamt) {
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; CHECK-LABEL: @t0_shl(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
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; CHECK-NEXT: [[R:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE1]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%shamt_wide = sext i8 %shamt to i32
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t1_lshr(i32 %x, i8 %shamt) {
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; CHECK-LABEL: @t1_lshr(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
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; CHECK-NEXT: [[R:%.*]] = lshr i32 [[X:%.*]], [[SHAMT_WIDE1]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%shamt_wide = sext i8 %shamt to i32
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%r = lshr i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @t2_ashr(i32 %x, i8 %shamt) {
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; CHECK-LABEL: @t2_ashr(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i8 [[SHAMT:%.*]] to i32
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[X:%.*]], [[SHAMT_WIDE1]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%shamt_wide = sext i8 %shamt to i32
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%r = ashr i32 %x, %shamt_wide
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ret i32 %r
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}
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define <2 x i32> @t3_vec_shl(<2 x i32> %x, <2 x i8> %shamt) {
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; CHECK-LABEL: @t3_vec_shl(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
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; CHECK-NEXT: [[R:%.*]] = shl <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%shamt_wide = sext <2 x i8> %shamt to <2 x i32>
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%r = shl <2 x i32> %x, %shamt_wide
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ret <2 x i32> %r
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}
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define <2 x i32> @t4_vec_lshr(<2 x i32> %x, <2 x i8> %shamt) {
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; CHECK-LABEL: @t4_vec_lshr(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
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; CHECK-NEXT: [[R:%.*]] = lshr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%shamt_wide = sext <2 x i8> %shamt to <2 x i32>
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%r = lshr <2 x i32> %x, %shamt_wide
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ret <2 x i32> %r
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}
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define <2 x i32> @t5_vec_ashr(<2 x i32> %x, <2 x i8> %shamt) {
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; CHECK-LABEL: @t5_vec_ashr(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext <2 x i8> [[SHAMT:%.*]] to <2 x i32>
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; CHECK-NEXT: [[R:%.*]] = ashr <2 x i32> [[X:%.*]], [[SHAMT_WIDE1]]
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; CHECK-NEXT: ret <2 x i32> [[R]]
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;
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%shamt_wide = sext <2 x i8> %shamt to <2 x i32>
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%r = ashr <2 x i32> %x, %shamt_wide
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ret <2 x i32> %r
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}
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define i32 @t6_twoshifts(i32 %x, i8 %shamt) {
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; CHECK-LABEL: @t6_twoshifts(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[SHAMT_WIDE:%.*]] = sext i8 [[SHAMT:%.*]] to i32
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; CHECK-NEXT: br label [[WORK:%.*]]
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; CHECK: work:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: [[N0:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[N0]], [[SHAMT_WIDE]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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bb:
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%shamt_wide = sext i8 %shamt to i32
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br label %work
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work:
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%n0 = shl i32 %x, %shamt_wide
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%r = ashr i32 %n0, %shamt_wide
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br label %end
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end:
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ret i32 %r
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}
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; This is not valid for funnel shifts in general
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declare i7 @llvm.fshl.i7(i7 %a, i7 %b, i7 %c)
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declare i7 @llvm.fshr.i7(i7 %a, i7 %b, i7 %c)
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define i7 @n7_fshl(i7 %x, i7 %y, i6 %shamt) {
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; CHECK-LABEL: @n7_fshl(
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; CHECK-NEXT: [[SHAMT_WIDE:%.*]] = sext i6 [[SHAMT:%.*]] to i7
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; CHECK-NEXT: [[R:%.*]] = call i7 @llvm.fshl.i7(i7 [[X:%.*]], i7 [[Y:%.*]], i7 [[SHAMT_WIDE]])
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; CHECK-NEXT: ret i7 [[R]]
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;
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%shamt_wide = sext i6 %shamt to i7
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%r = call i7 @llvm.fshl.i7(i7 %x, i7 %y, i7 %shamt_wide)
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ret i7 %r
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}
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define i7 @n8_fshr(i7 %x, i7 %y, i6 %shamt) {
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; CHECK-LABEL: @n8_fshr(
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; CHECK-NEXT: [[SHAMT_WIDE:%.*]] = sext i6 [[SHAMT:%.*]] to i7
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; CHECK-NEXT: [[R:%.*]] = call i7 @llvm.fshr.i7(i7 [[X:%.*]], i7 [[Y:%.*]], i7 [[SHAMT_WIDE]])
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; CHECK-NEXT: ret i7 [[R]]
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;
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%shamt_wide = sext i6 %shamt to i7
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%r = call i7 @llvm.fshr.i7(i7 %x, i7 %y, i7 %shamt_wide)
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ret i7 %r
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}
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; And the cases that are safe are handled by SimplifyDemandedBits().
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declare i8 @llvm.fshl.i8(i8 %a, i8 %b, i8 %c)
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declare i8 @llvm.fshr.i8(i8 %a, i8 %b, i8 %c)
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define i8 @t9_fshl(i8 %x, i8 %y, i6 %shamt) {
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; CHECK-LABEL: @t9_fshl(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i6 [[SHAMT:%.*]] to i8
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.fshl.i8(i8 [[X:%.*]], i8 [[Y:%.*]], i8 [[SHAMT_WIDE1]])
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; CHECK-NEXT: ret i8 [[R]]
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;
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%shamt_wide = sext i6 %shamt to i8
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%r = call i8 @llvm.fshl.i8(i8 %x, i8 %y, i8 %shamt_wide)
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ret i8 %r
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}
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define i8 @t10_fshr(i8 %x, i8 %y, i6 %shamt) {
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; CHECK-LABEL: @t10_fshr(
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; CHECK-NEXT: [[SHAMT_WIDE1:%.*]] = zext i6 [[SHAMT:%.*]] to i8
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; CHECK-NEXT: [[R:%.*]] = call i8 @llvm.fshr.i8(i8 [[X:%.*]], i8 [[Y:%.*]], i8 [[SHAMT_WIDE1]])
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; CHECK-NEXT: ret i8 [[R]]
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;
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%shamt_wide = sext i6 %shamt to i8
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%r = call i8 @llvm.fshr.i8(i8 %x, i8 %y, i8 %shamt_wide)
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ret i8 %r
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}
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declare void @use32(i32)
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define i32 @n11_extrause(i32 %x, i8 %shamt) {
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; CHECK-LABEL: @n11_extrause(
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; CHECK-NEXT: [[SHAMT_WIDE:%.*]] = sext i8 [[SHAMT:%.*]] to i32
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; CHECK-NEXT: call void @use32(i32 [[SHAMT_WIDE]])
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; CHECK-NEXT: [[R:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE]]
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; CHECK-NEXT: ret i32 [[R]]
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;
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%shamt_wide = sext i8 %shamt to i32
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call void @use32(i32 %shamt_wide)
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%r = shl i32 %x, %shamt_wide
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ret i32 %r
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}
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define i32 @n12_twoshifts_and_extrause(i32 %x, i8 %shamt) {
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; CHECK-LABEL: @n12_twoshifts_and_extrause(
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; CHECK-NEXT: [[SHAMT_WIDE:%.*]] = sext i8 [[SHAMT:%.*]] to i32
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; CHECK-NEXT: br label [[WORK:%.*]]
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; CHECK: work:
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; CHECK-NEXT: br label [[END:%.*]]
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; CHECK: end:
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; CHECK-NEXT: [[N0:%.*]] = shl i32 [[X:%.*]], [[SHAMT_WIDE]]
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; CHECK-NEXT: [[R:%.*]] = ashr i32 [[N0]], [[SHAMT_WIDE]]
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; CHECK-NEXT: call void @use32(i32 [[SHAMT_WIDE]])
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; CHECK-NEXT: ret i32 [[R]]
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;
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%shamt_wide = sext i8 %shamt to i32
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br label %work
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work:
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%n0 = shl i32 %x, %shamt_wide
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%r = ashr i32 %n0, %shamt_wide
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br label %end
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end:
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call void @use32(i32 %shamt_wide)
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ret i32 %r
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}
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