Justin Hibbits 98a532dd8e Add saving and restoring of r30 to the prologue and epilogue, respectively ... Summary: The PIC additions didn't update the prologue and epilogue code to save and restore r30 (PIC base register). This does that. Test Plan: Tests updated. Reviewers: hfinkel Reviewed By: hfinkel Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6876 llvm-svn: 225450		2015-01-08 15:47:19 +00:00
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AArch64	Revert r225165 and r225169	2015-01-07 06:34:34 +00:00
ARM	Fix large stack alignment codegen for ARM and Thumb2 targets	2015-01-08 15:09:14 +00:00
CPP	IR: add "cmpxchg weak" variant to support permitted failure.	2014-06-13 14:24:07 +00:00
Generic	CodeGen: do not attempt to invalidate virtual registers for zero-sized phis.	2014-12-19 20:50:07 +00:00
Hexagon	[Hexagon] Adding dealloc_return encoding and absolute address stores.	2015-01-06 16:15:15 +00:00
Inputs	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
Mips	[mips][microMIPS] Fix bugs related to atomic SC/LL instructions	2014-12-18 16:39:29 +00:00
NVPTX	[NVPTX] Fix bugs related to isSingleValueType	2014-12-17 17:59:04 +00:00
PowerPC	Add saving and restoring of r30 to the prologue and epilogue, respectively	2015-01-08 15:47:19 +00:00
R600	R600/SI: Remove SIISelLowering::legalizeOperands()	2015-01-08 15:08:17 +00:00
SPARC	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
SystemZ	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00
Thumb2	Fix large stack alignment codegen for ARM and Thumb2 targets	2015-01-08 15:09:14 +00:00
X86	Masked Load/Store - fixed a bug in type legalization.	2015-01-08 12:29:19 +00:00
XCore	IR: Make metadata typeless in assembly	2014-12-15 19:07:53 +00:00