forked from OSchip/llvm-project
153 lines
6.5 KiB
C
153 lines
6.5 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -mvscale-min=4 -mvscale-max=4 -fallow-half-arguments-and-returns -S -O1 -emit-llvm -o - %s | FileCheck %s
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// REQUIRES: aarch64-registered-target
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#include <arm_sve.h>
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#define N __ARM_FEATURE_SVE_BITS
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typedef svint32_t fixed_int32_t __attribute__((arm_sve_vector_bits(N)));
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typedef svfloat64_t fixed_float64_t __attribute__((arm_sve_vector_bits(N)));
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typedef svbool_t fixed_bool_t __attribute__((arm_sve_vector_bits(N)));
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//===----------------------------------------------------------------------===//
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// Test caller/callee with VLST <-> VLAT
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @sizeless_callee(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 4 x i32> [[X:%.*]]
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//
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svint32_t sizeless_callee(svint32_t x) {
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return x;
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}
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// CHECK-LABEL: @fixed_caller(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 4 x i32> [[X_COERCE:%.*]]
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//
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fixed_int32_t fixed_caller(fixed_int32_t x) {
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return sizeless_callee(x);
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}
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// CHECK-LABEL: @fixed_callee(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: ret <vscale x 4 x i32> [[X_COERCE:%.*]]
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//
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fixed_int32_t fixed_callee(fixed_int32_t x) {
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return x;
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}
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// CHECK-LABEL: @sizeless_caller(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[COERCE1:%.*]] = alloca <16 x i32>, align 16
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast <16 x i32>* [[COERCE1]] to <vscale x 4 x i32>*
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// CHECK-NEXT: store <vscale x 4 x i32> [[X:%.*]], <vscale x 4 x i32>* [[TMP0]], align 16
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// CHECK-NEXT: [[TMP1:%.*]] = load <16 x i32>, <16 x i32>* [[COERCE1]], align 16, !tbaa [[TBAA6:![0-9]+]]
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// CHECK-NEXT: [[CASTSCALABLESVE2:%.*]] = call <vscale x 4 x i32> @llvm.experimental.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> undef, <16 x i32> [[TMP1]], i64 0)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[CASTSCALABLESVE2]]
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//
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svint32_t sizeless_caller(svint32_t x) {
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return fixed_callee(x);
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}
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//===----------------------------------------------------------------------===//
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// fixed, fixed
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @call_int32_ff(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1_COERCE:%.*]], <vscale x 4 x i32> [[OP2_COERCE:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
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//
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fixed_int32_t call_int32_ff(svbool_t pg, fixed_int32_t op1, fixed_int32_t op2) {
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return svsel(pg, op1, op2);
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}
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// CHECK-LABEL: @call_float64_ff(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1_COERCE:%.*]], <vscale x 2 x double> [[OP2_COERCE:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
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//
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fixed_float64_t call_float64_ff(svbool_t pg, fixed_float64_t op1, fixed_float64_t op2) {
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return svsel(pg, op1, op2);
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}
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// CHECK-LABEL: @call_bool_ff(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP2:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[TMP1:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
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//
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fixed_bool_t call_bool_ff(svbool_t pg, fixed_bool_t op1, fixed_bool_t op2) {
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return svsel(pg, op1, op2);
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}
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//===----------------------------------------------------------------------===//
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// fixed, scalable
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @call_int32_fs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1_COERCE:%.*]], <vscale x 4 x i32> [[OP2:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
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//
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fixed_int32_t call_int32_fs(svbool_t pg, fixed_int32_t op1, svint32_t op2) {
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return svsel(pg, op1, op2);
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}
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// CHECK-LABEL: @call_float64_fs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1_COERCE:%.*]], <vscale x 2 x double> [[OP2:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
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//
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fixed_float64_t call_float64_fs(svbool_t pg, fixed_float64_t op1, svfloat64_t op2) {
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return svsel(pg, op1, op2);
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}
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// CHECK-LABEL: @call_bool_fs(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[TMP0:%.*]], <vscale x 16 x i1> [[OP2:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP1]]
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//
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fixed_bool_t call_bool_fs(svbool_t pg, fixed_bool_t op1, svbool_t op2) {
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return svsel(pg, op1, op2);
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}
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//===----------------------------------------------------------------------===//
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// scalable, scalable
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//===----------------------------------------------------------------------===//
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// CHECK-LABEL: @call_int32_ss(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> [[PG:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP1:%.*]], <vscale x 4 x i32> [[OP2:%.*]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
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//
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fixed_int32_t call_int32_ss(svbool_t pg, svint32_t op1, svint32_t op2) {
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return svsel(pg, op1, op2);
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}
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// CHECK-LABEL: @call_float64_ss(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> [[PG:%.*]])
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// CHECK-NEXT: [[TMP1:%.*]] = select <vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]]
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// CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
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//
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fixed_float64_t call_float64_ss(svbool_t pg, svfloat64_t op1, svfloat64_t op2) {
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return svsel(pg, op1, op2);
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}
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// CHECK-LABEL: @call_bool_ss(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = select <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP2:%.*]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
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//
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fixed_bool_t call_bool_ss(svbool_t pg, svbool_t op1, svbool_t op2) {
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return svsel(pg, op1, op2);
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}
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