forked from OSchip/llvm-project
160 lines
6.0 KiB
C++
160 lines
6.0 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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// RUN: %clang_cc1 -triple thumbv8.1m.main-none-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
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// REQUIRES: aarch64-registered-target || arm-registered-target
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#include <arm_mve.h>
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// CHECK-LABEL: @_Z16test_vbicq_n_s1617__simd128_int16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], <i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007, i16 11007>
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// CHECK-NEXT: ret <8 x i16> [[TMP0]]
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//
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int16x8_t test_vbicq_n_s16(int16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vbicq(a, 0xd500);
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#else /* POLYMORPHIC */
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return vbicq_n_s16(a, 0xd500);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z16test_vbicq_n_u3218__simd128_uint32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], <i32 -8193, i32 -8193, i32 -8193, i32 -8193>
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// CHECK-NEXT: ret <4 x i32> [[TMP0]]
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//
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uint32x4_t test_vbicq_n_u32(uint32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vbicq(a, 0x2000);
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#else /* POLYMORPHIC */
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return vbicq_n_u32(a, 0x2000);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z16test_vorrq_n_s3217__simd128_int32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], <i32 65536, i32 65536, i32 65536, i32 65536>
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// CHECK-NEXT: ret <4 x i32> [[TMP0]]
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//
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int32x4_t test_vorrq_n_s32(int32x4_t a)
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{
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#ifdef POLYMORPHIC
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return vorrq(a, 0x10000);
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#else /* POLYMORPHIC */
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return vorrq_n_s32(a, 0x10000);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z16test_vorrq_n_u1618__simd128_uint16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], <i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096, i16 -4096>
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// CHECK-NEXT: ret <8 x i16> [[TMP0]]
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//
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uint16x8_t test_vorrq_n_u16(uint16x8_t a)
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{
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#ifdef POLYMORPHIC
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return vorrq(a, 0xf000);
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#else /* POLYMORPHIC */
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return vorrq_n_u16(a, 0xf000);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z16test_vcmpeqq_f1619__simd128_float16_tS_(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = fcmp oeq <8 x half> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: ret i16 [[TMP2]]
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//
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mve_pred16_t test_vcmpeqq_f16(float16x8_t a, float16x8_t b)
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{
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#ifdef POLYMORPHIC
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return vcmpeqq(a, b);
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#else /* POLYMORPHIC */
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return vcmpeqq_f16(a, b);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z18test_vcmpeqq_n_f1619__simd128_float16_tDh(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x half> poison, half [[B:%.*]], i32 0
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// CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x half> [[DOTSPLATINSERT]], <8 x half> poison, <8 x i32> zeroinitializer
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// CHECK-NEXT: [[TMP0:%.*]] = fcmp oeq <8 x half> [[A:%.*]], [[DOTSPLAT]]
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// CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1> [[TMP0]])
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// CHECK-NEXT: [[TMP2:%.*]] = trunc i32 [[TMP1]] to i16
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// CHECK-NEXT: ret i16 [[TMP2]]
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//
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mve_pred16_t test_vcmpeqq_n_f16(float16x8_t a, float16_t b)
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{
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#ifdef POLYMORPHIC
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return vcmpeqq(a, b);
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#else /* POLYMORPHIC */
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return vcmpeqq_n_f16(a, b);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z14test_vld1q_u16PKt(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast i16* [[BASE:%.*]] to <8 x i16>*
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// CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, <8 x i16>* [[TMP0]], align 2
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// CHECK-NEXT: ret <8 x i16> [[TMP1]]
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//
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uint16x8_t test_vld1q_u16(const uint16_t *base)
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{
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#ifdef POLYMORPHIC
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return vld1q(base);
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#else /* POLYMORPHIC */
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return vld1q_u16(base);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z16test_vst1q_p_s32Pi17__simd128_int32_tt(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = bitcast i32* [[BASE:%.*]] to <4 x i32>*
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// CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[P:%.*]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP1]])
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// CHECK-NEXT: call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> [[VALUE:%.*]], <4 x i32>* [[TMP0]], i32 4, <4 x i1> [[TMP2]])
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// CHECK-NEXT: ret void
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//
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void test_vst1q_p_s32(int32_t *base, int32x4_t value, mve_pred16_t p)
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{
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#ifdef POLYMORPHIC
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vst1q_p(base, value, p);
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#else /* POLYMORPHIC */
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vst1q_p_s32(base, value, p);
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#endif /* POLYMORPHIC */
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}
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// CHECK-LABEL: @_Z30test_vldrdq_gather_base_wb_s64P18__simd128_uint64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* [[ADDR:%.*]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.v2i64.v2i64(<2 x i64> [[TMP0]], i32 576)
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// CHECK-NEXT: [[TMP2:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 1
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// CHECK-NEXT: store <2 x i64> [[TMP2]], <2 x i64>* [[ADDR]], align 8
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// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { <2 x i64>, <2 x i64> } [[TMP1]], 0
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// CHECK-NEXT: ret <2 x i64> [[TMP3]]
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//
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int64x2_t test_vldrdq_gather_base_wb_s64(uint64x2_t *addr)
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{
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return vldrdq_gather_base_wb_s64(addr, 0x240);
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}
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// CHECK-LABEL: @_Z31test_vstrwq_scatter_base_wb_u32P18__simd128_uint32_tS_(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, <4 x i32>* [[ADDR:%.*]], align 8
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// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4i32(<4 x i32> [[TMP0]], i32 64, <4 x i32> [[VALUE:%.*]])
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// CHECK-NEXT: store <4 x i32> [[TMP1]], <4 x i32>* [[ADDR]], align 8
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// CHECK-NEXT: ret void
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//
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void test_vstrwq_scatter_base_wb_u32(uint32x4_t *addr, uint32x4_t value)
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{
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#ifdef POLYMORPHIC
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vstrwq_scatter_base_wb(addr, 0x40, value);
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#else /* POLYMORPHIC */
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vstrwq_scatter_base_wb_u32(addr, 0x40, value);
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#endif /* POLYMORPHIC */
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}
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