forked from OSchip/llvm-project
52 lines
2.4 KiB
LLVM
52 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X86
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skylake | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=skx | FileCheck %s --check-prefix=X64
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define void @fetch_r16g16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32], [128 x i64] }*) nounwind {
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; X86-LABEL: fetch_r16g16_snorm_unorm8:
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; X86: # %bb.0: # %entry
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; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X86-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X86-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; X86-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
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; X86-NEXT: vpsrlw $7, %xmm0, %xmm0
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; X86-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u]
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; X86-NEXT: vmovd %xmm0, %ecx
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; X86-NEXT: orl $-16777216, %ecx # imm = 0xFF000000
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; X86-NEXT: movl %ecx, (%eax)
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; X86-NEXT: retl
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;
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; X64-LABEL: fetch_r16g16_snorm_unorm8:
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; X64: # %bb.0: # %entry
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; X64-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero
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; X64-NEXT: vpxor %xmm1, %xmm1, %xmm1
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; X64-NEXT: vpmaxsw %xmm1, %xmm0, %xmm0
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; X64-NEXT: vpsrlw $7, %xmm0, %xmm0
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; X64-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,2],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u]
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; X64-NEXT: vmovd %xmm0, %eax
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; X64-NEXT: orl $-16777216, %eax # imm = 0xFF000000
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; X64-NEXT: movl %eax, (%rdi)
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; X64-NEXT: retq
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entry:
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%5 = bitcast i8* %1 to <2 x i16>*
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%6 = load <2 x i16>, <2 x i16>* %5, align 2
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%7 = shufflevector <2 x i16> %6, <2 x i16> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
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%8 = icmp sgt <4 x i16> %7, zeroinitializer
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%9 = select <4 x i1> %8, <4 x i16> %7, <4 x i16> zeroinitializer
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%10 = lshr <4 x i16> %9, <i16 7, i16 7, i16 7, i16 7>
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%11 = shufflevector <4 x i16> %10, <4 x i16> undef, <2 x i32> <i32 0, i32 1>
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%12 = shufflevector <4 x i16> %10, <4 x i16> undef, <2 x i32> <i32 2, i32 3>
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%13 = bitcast <2 x i16> %11 to <4 x i8>
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%14 = bitcast <2 x i16> %12 to <4 x i8>
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%15 = shufflevector <4 x i8> %13, <4 x i8> %14, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
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%16 = bitcast <4 x i8> %15 to i32
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%17 = and i32 %16, 65535
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%18 = or i32 %17, -16777216
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%19 = bitcast <4 x i8>* %0 to i32*
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store i32 %18, i32* %19, align 4
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ret void
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}
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