forked from OSchip/llvm-project
74 lines
2.9 KiB
LLVM
74 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-- -mcpu=corei7 | FileCheck %s
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define signext i16 @t(i16* %qmatrix, i16* %dct, i16* %acBaseTable, i16* %acExtTable, i16 signext %acBaseRes, i16 signext %acMaskRes, i16 signext %acExtRes, i32* %bitptr, i32* %source, i32 %markerPrefix, i8** %byteptr, i32 %scale, i32 %round, i32 %bits) {
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; CHECK-LABEL: t:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %eax
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; CHECK-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; CHECK-NEXT: .p2align 4, 0x90
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; CHECK-NEXT: .LBB0_1: # %cond_next127
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; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: movl %eax, %edx
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; CHECK-NEXT: sarl %cl, %edx
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; CHECK-NEXT: incl %edx
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; CHECK-NEXT: cmpl $63, %edx
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; CHECK-NEXT: jb .LBB0_1
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; CHECK-NEXT: # %bb.2: # %UnifiedReturnBlock
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; CHECK-NEXT: xorl %eax, %eax
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; CHECK-NEXT: retl
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entry:
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br label %cond_next127
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cond_next127: ; preds = %cond_next391, %entry
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%tmp151 = add i32 0, %round ; <i32> [#uses=1]
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%tmp153 = ashr i32 %tmp151, %scale ; <i32> [#uses=1]
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%tmp158 = xor i32 0, %tmp153 ; <i32> [#uses=1]
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%tmp160 = or i32 %tmp158, 0 ; <i32> [#uses=1]
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%tmp180181 = sext i16 0 to i32 ; <i32> [#uses=1]
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%tmp183 = add i32 %tmp160, 1 ; <i32> [#uses=1]
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br i1 false, label %cond_true188, label %cond_next245
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cond_true188: ; preds = %cond_next127
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ret i16 0
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cond_next245: ; preds = %cond_next127
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%tmp253444 = lshr i32 %tmp180181, 4 ; <i32> [#uses=1]
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%tmp254 = and i32 %tmp253444, 15 ; <i32> [#uses=1]
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br i1 false, label %cond_true267, label %cond_next391
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cond_true267: ; preds = %cond_next245
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%tmp269 = load i8*, i8** %byteptr, align 4 ; <i8*> [#uses=3]
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%tmp270 = load i8, i8* %tmp269, align 1 ; <i8> [#uses=1]
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%tmp270271 = zext i8 %tmp270 to i32 ; <i32> [#uses=1]
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%tmp272 = getelementptr i8, i8* %tmp269, i32 1 ; <i8*> [#uses=2]
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store i8* %tmp272, i8** %byteptr, align 4
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%tmp276 = load i8, i8* %tmp272, align 1 ; <i8> [#uses=1]
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%tmp278 = getelementptr i8, i8* %tmp269, i32 2 ; <i8*> [#uses=1]
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store i8* %tmp278, i8** %byteptr, align 4
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%tmp286 = icmp eq i32 %tmp270271, %markerPrefix ; <i1> [#uses=1]
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%cond = icmp eq i8 %tmp276, 0 ; <i1> [#uses=1]
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%bothcond = and i1 %tmp286, %cond ; <i1> [#uses=1]
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br i1 %bothcond, label %cond_true294, label %cond_next327
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cond_true294: ; preds = %cond_true267
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ret i16 0
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cond_next327: ; preds = %cond_true267
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br i1 false, label %cond_true343, label %cond_next391
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cond_true343: ; preds = %cond_next327
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%tmp345 = load i8*, i8** %byteptr, align 4 ; <i8*> [#uses=1]
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store i8* null, i8** %byteptr, align 4
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store i8* %tmp345, i8** %byteptr, align 4
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br label %cond_next391
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cond_next391: ; preds = %cond_true343, %cond_next327, %cond_next245
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%tmp422445 = add i32 %tmp254, %tmp183 ; <i32> [#uses=1]
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%tmp429448 = icmp ult i32 %tmp422445, 63 ; <i1> [#uses=1]
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br i1 %tmp429448, label %cond_next127, label %UnifiedReturnBlock
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UnifiedReturnBlock: ; preds = %cond_next391
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ret i16 0
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}
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