llvm-project/llvm/test/MC/Disassembler/X86
Craig Topper e268598dd3 [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling for prefetch instructions.
Previously prefetch was only considered legal if sse was enabled, but it should be supported with 3dnow as well.

The prfchw flag now imply at least some form of prefetch without the write hint is available, either the sse or 3dnow version. This is true even if 3dnow and sse are explicitly disabled.

Similarly prefetchwt1 feature implies availability of prefetchw and the the prefetcht0/1/2/nta instructions. This way we can support _MM_HINT_ET0 using prefetchw and _MM_HINT_ET1 with prefetchwt1. And its assumed that if we have levels for the write hint we would have levels for the non-write hint, thus why we enable the sse prefetch instructions.

I believe this behavior is consistent with gcc. I've updated the prefetch.ll to test all of these combinations.

llvm-svn: 321335
2017-12-22 02:30:30 +00:00
..
avx-512.txt [X86] Fix disassembly of EVEX rounding control and SAE instructions. 2017-10-23 02:26:24 +00:00
fp-stack.txt [X86] Run dos2unix on two disassembler tests. 2017-10-02 21:46:58 +00:00
gather-novsib.txt [X86] Don't allow gather/scatter to disassembler if memory operand does not use a SIB byte. 2017-10-22 04:32:30 +00:00
hex-immediates.txt
intel-syntax-32.txt
intel-syntax.txt
invalid-VEX-vvvv.txt
lit.local.cfg
marked-up.txt
missing-sib.txt
moffs.txt
padlock.txt
prefixes-i386.txt Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
prefixes-x86_64.txt Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
prefixes.txt [MC][X86] Add test case from PR19251 2017-11-18 23:23:25 +00:00
simple-tests.txt Fix for Bug 34475 - LOCK/REP/REPNE prefixes emitted as instruction on their own. 2017-11-03 15:25:13 +00:00
truncated-input.txt
x86-16.txt Avoid unecessary opsize byte in segment move to memory 2017-11-21 19:28:13 +00:00
x86-32.txt [X86] Add prefetchwt1 instruction and overhaul priorities and isel enabling for prefetch instructions. 2017-12-22 02:30:30 +00:00
x86-64-err.txt [X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored. 2017-10-22 06:18:26 +00:00
x86-64.txt [MC][X86] Add teet case from PR32807 2017-11-18 23:06:42 +00:00