llvm-project/llvm/test/CodeGen
Krzysztof Parzyszek f9d01a12d1 [Hexagon] Add patterns for truncating HVX vector types
Only non-bool vectors.

llvm-svn: 321895
2018-01-05 20:48:03 +00:00
..
AArch64 [AArch64] Fix -mcpu option in aarch64-combine-fmul-fsub.mir (NFC) 2018-01-05 11:17:48 +00:00
AMDGPU StructurizeCFG: Fix broken backedge detection 2018-01-03 18:45:37 +00:00
ARC
ARM [DAGCombine] Fix for PR37563 2018-01-05 08:47:23 +00:00
AVR [AVR] Fix two CodeGen tests 2017-12-09 07:51:43 +00:00
BPF bpf: add support for objdump -print-imm-hex 2017-12-20 19:39:58 +00:00
Generic [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Hexagon [Hexagon] Add patterns for truncating HVX vector types 2018-01-05 20:48:03 +00:00
Inputs
Lanai [CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register. 2017-12-07 10:40:31 +00:00
MIR [YAML] Add support for non-printable characters 2017-12-18 17:38:03 +00:00
MSP430 [CodeGen] Unify MBB reference format in both MIR and debug output 2017-12-04 17:18:51 +00:00
Mips [mips] Replace assert by an error message 2017-12-29 19:18:24 +00:00
NVPTX [DEBUG] Add initial tests for debug info for NVPTX target, NFC. 2018-01-04 21:07:07 +00:00
Nios2 [Nios2] final infrastructure to provide compilation of a return from a function 2017-12-07 12:35:02 +00:00
PowerPC [PowerPC] fix a bug in TCO eligibility check 2017-12-30 08:09:04 +00:00
RISCV [RISCV] Enable emission of alias instructions by default 2017-12-15 09:47:01 +00:00
SPARC Revert r318704 - [Sparc] efficient pattern for UINT_TO_FP conversion 2017-12-11 22:25:04 +00:00
SystemZ [MachineOperand][MIR] Add isRenamable to MachineOperand. 2017-12-12 17:53:59 +00:00
Thumb [ARM] Add tests for D34515 2017-12-15 09:24:46 +00:00
Thumb2 [ARM] Register the Thumb2SizeReducePass. NFC 2017-12-19 12:19:08 +00:00
WebAssembly [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors 2017-12-15 00:17:10 +00:00
WinEH
X86 [X86] Regenerate illegal move test 2018-01-05 14:24:03 +00:00
XCore