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llvm-project/mlir
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River Riddle 5d699d18b3 [mlir] Remove locking for dialect/operation registration. 
Moving forward dialects should only be registered in a thread safe context. This matches the existing usage we have today, but it allows for removing quite a bit of expensive locking from the context.

This led to ~.5 a second compile time improvement when running one conversion pass on a very large .mlir file(hundreds of thousands of operations).

Differential Revision: https://reviews.llvm.org/D82595
 		2020-06-30 15:52:33 -07:00
..
cmake/modules Install the MLIRTableGen static library. 2020-06-11 18:23:24 -07:00
docs [mlir] Refactor InterfaceGen to support generating interfaces for Attributes and Types. 2020-06-30 15:52:33 -07:00
examples [MLIR] Add variadic isa<> for Type, Value, and Attribute 2020-06-29 15:04:48 -07:00
include [mlir] Remove locking for dialect/operation registration. 2020-06-30 15:52:33 -07:00
integration_test [mlir] [VectorOps] Extend vector reduction integration test with reassoc=true cases. 2020-06-29 13:28:20 -07:00
lib [mlir] Remove locking for dialect/operation registration. 2020-06-30 15:52:33 -07:00
test [mlir] Refactor InterfaceGen to support generating interfaces for Attributes and Types. 2020-06-30 15:52:33 -07:00
tools [mlir] Refactor InterfaceGen to support generating interfaces for Attributes and Types. 2020-06-30 15:52:33 -07:00
unittests [mlir-tblgen] Use fully qualified names in generated code files 2020-06-26 15:05:33 +02:00
utils [MLIR][SPIRV] Extend automation script to generate coverage report. 2020-06-23 11:42:59 -04:00
.clang-format [mlir] add .clang-format 2019-03-29 12:41:43 -07:00
.clang-tidy Fix MLIR clang-tidy: when tweaking it does not inherit from the parent 2020-03-07 17:44:21 +00:00
CMakeLists.txt [mlir] [integration_test] Make integration tests default OFF 2020-06-15 14:33:18 -07:00
LICENSE.TXT Add the Apache2 with LLVM exceptions license to MLIR 2019-12-24 00:58:06 -08:00
README.md mlir README.md: Fix the syntax 2019-12-24 13:31:07 +01:00

README.md

Multi-Level Intermediate Representation

See https://mlir.llvm.org/ for more information.