forked from OSchip/llvm-project
63 lines
2.1 KiB
C++
63 lines
2.1 KiB
C++
//===- AMDGPUGlobalISelUtils -------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
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#define LLVM_LIB_TARGET_AMDGPU_AMDGPUGLOBALISELUTILS_H
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#include "AMDGPUInstrInfo.h"
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#include "llvm/CodeGen/Register.h"
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#include <tuple>
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namespace llvm {
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class MachineInstr;
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class MachineRegisterInfo;
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namespace AMDGPU {
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/// Returns Base register, constant offset, and offset def point.
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std::tuple<Register, unsigned, MachineInstr *>
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getBaseWithConstantOffset(MachineRegisterInfo &MRI, Register Reg);
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bool isLegalVOP3PShuffleMask(ArrayRef<int> Mask);
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/// Return number of address arguments, and the number of gradients for an image
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/// intrinsic.
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inline std::pair<int, int>
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getImageNumVAddr(const AMDGPU::ImageDimIntrinsicInfo *ImageDimIntr,
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const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode) {
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const AMDGPU::MIMGDimInfo *DimInfo
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= AMDGPU::getMIMGDimInfo(ImageDimIntr->Dim);
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int NumGradients = BaseOpcode->Gradients ? DimInfo->NumGradients : 0;
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int NumCoords = BaseOpcode->Coordinates ? DimInfo->NumCoords : 0;
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int NumLCM = BaseOpcode->LodOrClampOrMip ? 1 : 0;
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int NumVAddr = BaseOpcode->NumExtraArgs + NumGradients + NumCoords + NumLCM;
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return {NumVAddr, NumGradients};
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}
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/// Return index of dmask in an gMIR image intrinsic
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inline int getDMaskIdx(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
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int NumDefs) {
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assert(!BaseOpcode->Atomic);
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return NumDefs + 1 + (BaseOpcode->Store ? 1 : 0);
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}
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/// Return first address operand index in a gMIR image intrinsic.
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inline int getImageVAddrIdxBegin(const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode,
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int NumDefs) {
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if (BaseOpcode->Atomic)
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return NumDefs + 1 + (BaseOpcode->AtomicX2 ? 2 : 1);
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return getDMaskIdx(BaseOpcode, NumDefs) + 1;
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}
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}
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}
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#endif
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