forked from OSchip/llvm-project
197 lines
7.6 KiB
LLVM
197 lines
7.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --include-generated-funcs
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; RUN: opt -S -verify -iroutliner -ir-outlining-no-cost < %s | FileCheck %s
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; Here we have multiple exits, but different sources, and only one has an
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; output set. We check to make sure that we do not generated extra output
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; blocks or entries in the switch statement.
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define void @outline_outputs1() #0 {
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entry:
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%output = alloca i32, align 4
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%result = alloca i32, align 4
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%output2 = alloca i32, align 4
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%result2 = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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br label %block_2
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block_1:
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%a2 = alloca i32, align 4
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%b2 = alloca i32, align 4
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br label %block_2
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block_2:
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%a2val = load i32, i32* %a
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%b2val = load i32, i32* %b
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%add2 = add i32 2, %a2val
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%mul2 = mul i32 2, %b2val
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br label %block_5
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block_3:
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%aval = load i32, i32* %a
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%bval = load i32, i32* %b
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%add = add i32 2, %aval
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%mul = mul i32 2, %bval
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br label %block_4
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block_4:
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store i32 %add, i32* %output, align 4
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store i32 %mul, i32* %result, align 4
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br label %block_6
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block_5:
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store i32 %add2, i32* %output, align 4
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store i32 %mul2, i32* %result, align 4
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br label %block_7
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block_6:
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ret void
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block_7:
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ret void
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}
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define void @outline_outputs2() #0 {
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entry:
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%output = alloca i32, align 4
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%result = alloca i32, align 4
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%output2 = alloca i32, align 4
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%result2 = alloca i32, align 4
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%a = alloca i32, align 4
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%b = alloca i32, align 4
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br label %block_2
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block_1:
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%a2 = alloca i32, align 4
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%b2 = alloca i32, align 4
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br label %block_2
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block_2:
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%a2val = load i32, i32* %a
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%b2val = load i32, i32* %b
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%add2 = add i32 2, %a2val
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%mul2 = mul i32 2, %b2val
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br label %block_5
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block_3:
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%aval = load i32, i32* %a
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%bval = load i32, i32* %b
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%add = add i32 2, %aval
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%mul = mul i32 2, %bval
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br label %block_4
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block_4:
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store i32 %add, i32* %output, align 4
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store i32 %mul, i32* %result, align 4
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br label %block_7
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block_5:
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store i32 %add2, i32* %output, align 4
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store i32 %mul2, i32* %result, align 4
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br label %block_6
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block_6:
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%diff = sub i32 %a2val, %b2val
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ret void
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block_7:
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%quot = udiv i32 %add, %mul
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ret void
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}
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; CHECK-LABEL: @outline_outputs1(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2:%.*]]
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; CHECK: block_1:
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; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2]]
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; CHECK: block_2:
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; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[OUTPUT]], i32* [[RESULT]], i32* null, i32* null, i32* null, i32* null, i32 -1)
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; CHECK-NEXT: br i1 [[TMP0]], label [[BLOCK_6:%.*]], label [[BLOCK_7:%.*]]
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; CHECK: block_6:
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; CHECK-NEXT: ret void
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; CHECK: block_7:
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; CHECK-NEXT: ret void
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;
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;
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; CHECK-LABEL: @outline_outputs2(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[MUL_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[ADD_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B2VAL_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[A2VAL_LOC:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[OUTPUT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[OUTPUT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[RESULT2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[A:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2:%.*]]
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; CHECK: block_1:
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; CHECK-NEXT: [[A2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: [[B2:%.*]] = alloca i32, align 4
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; CHECK-NEXT: br label [[BLOCK_2]]
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; CHECK: block_2:
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; CHECK-NEXT: [[LT_CAST:%.*]] = bitcast i32* [[A2VAL_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: [[LT_CAST1:%.*]] = bitcast i32* [[B2VAL_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST1]])
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; CHECK-NEXT: [[LT_CAST2:%.*]] = bitcast i32* [[ADD_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST2]])
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; CHECK-NEXT: [[LT_CAST3:%.*]] = bitcast i32* [[MUL_LOC]] to i8*
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; CHECK-NEXT: call void @llvm.lifetime.start.p0i8(i64 -1, i8* [[LT_CAST3]])
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; CHECK-NEXT: [[TMP0:%.*]] = call i1 @outlined_ir_func_0(i32* [[A]], i32* [[B]], i32* [[OUTPUT]], i32* [[RESULT]], i32* [[A2VAL_LOC]], i32* [[B2VAL_LOC]], i32* [[ADD_LOC]], i32* [[MUL_LOC]], i32 0)
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; CHECK-NEXT: [[A2VAL_RELOAD:%.*]] = load i32, i32* [[A2VAL_LOC]], align 4
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; CHECK-NEXT: [[B2VAL_RELOAD:%.*]] = load i32, i32* [[B2VAL_LOC]], align 4
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; CHECK-NEXT: [[ADD_RELOAD:%.*]] = load i32, i32* [[ADD_LOC]], align 4
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; CHECK-NEXT: [[MUL_RELOAD:%.*]] = load i32, i32* [[MUL_LOC]], align 4
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST]])
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST1]])
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST2]])
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; CHECK-NEXT: call void @llvm.lifetime.end.p0i8(i64 -1, i8* [[LT_CAST3]])
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; CHECK-NEXT: br i1 [[TMP0]], label [[BLOCK_7:%.*]], label [[BLOCK_6:%.*]]
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; CHECK: block_6:
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; CHECK-NEXT: [[DIFF:%.*]] = sub i32 [[A2VAL_RELOAD]], [[B2VAL_RELOAD]]
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; CHECK-NEXT: ret void
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; CHECK: block_7:
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; CHECK-NEXT: [[QUOT:%.*]] = udiv i32 [[ADD_RELOAD]], [[MUL_RELOAD]]
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; CHECK-NEXT: ret void
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;
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;
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; CHECK: define internal i1 @outlined_ir_func_0(
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; CHECK-NEXT: newFuncRoot:
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; CHECK-NEXT: br label [[BLOCK_2_TO_OUTLINE:%.*]]
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; CHECK: block_2_to_outline:
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; CHECK-NEXT: [[A2VAL:%.*]] = load i32, i32* [[TMP0:%.*]], align 4
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; CHECK-NEXT: [[B2VAL:%.*]] = load i32, i32* [[TMP1:%.*]], align 4
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; CHECK-NEXT: [[ADD2:%.*]] = add i32 2, [[A2VAL]]
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; CHECK-NEXT: [[MUL2:%.*]] = mul i32 2, [[B2VAL]]
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; CHECK-NEXT: br label [[BLOCK_5:%.*]]
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; CHECK: block_3:
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; CHECK-NEXT: [[AVAL:%.*]] = load i32, i32* [[TMP0]], align 4
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; CHECK-NEXT: [[BVAL:%.*]] = load i32, i32* [[TMP1]], align 4
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; CHECK-NEXT: [[ADD:%.*]] = add i32 2, [[AVAL]]
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; CHECK-NEXT: [[MUL:%.*]] = mul i32 2, [[BVAL]]
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; CHECK-NEXT: br label [[BLOCK_4:%.*]]
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; CHECK: block_4:
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; CHECK-NEXT: store i32 [[ADD]], i32* [[TMP2:%.*]], align 4
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; CHECK-NEXT: store i32 [[MUL]], i32* [[TMP3:%.*]], align 4
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; CHECK-NEXT: br label [[BLOCK_6_EXITSTUB:%.*]]
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; CHECK: block_5:
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; CHECK-NEXT: store i32 [[ADD2]], i32* [[TMP2]], align 4
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; CHECK-NEXT: store i32 [[MUL2]], i32* [[TMP3]], align 4
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; CHECK-NEXT: br label [[BLOCK_7_EXITSTUB:%.*]]
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; CHECK: block_6.exitStub:
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; CHECK-NEXT: switch i32 [[TMP8:%.*]], label [[FINAL_BLOCK_1:%.*]] [
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; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_1_1:%.*]]
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; CHECK-NEXT: ]
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; CHECK: block_7.exitStub:
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; CHECK-NEXT: switch i32 [[TMP8]], label [[FINAL_BLOCK_0:%.*]] [
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; CHECK-NEXT: i32 0, label [[OUTPUT_BLOCK_1_0:%.*]]
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; CHECK-NEXT: ]
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; CHECK: output_block_1_0:
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; CHECK-NEXT: store i32 [[A2VAL]], i32* [[TMP4:%.*]], align 4
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; CHECK-NEXT: store i32 [[B2VAL]], i32* [[TMP5:%.*]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_0]]
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; CHECK: output_block_1_1:
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; CHECK-NEXT: store i32 [[ADD]], i32* [[TMP6:%.*]], align 4
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; CHECK-NEXT: store i32 [[MUL]], i32* [[TMP7:%.*]], align 4
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; CHECK-NEXT: br label [[FINAL_BLOCK_1]]
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; CHECK: final_block_0:
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; CHECK-NEXT: ret i1 false
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; CHECK: final_block_1:
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; CHECK-NEXT: ret i1 true
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;
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